From 1bb86cfffe36a31422efcfe2e7946cf151d5c30f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Jul 2019 09:49:12 -0700 Subject: [PATCH 01/22] updated boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 84879571..51bfc070 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 848795715f721b6a88887283179176474a1496b8 +Subproject commit 51bfc070e8b4750f5401b5db235233421ab8deba From ce0806a37148c180edad177d5e41c5169ca8720d Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 24 Jul 2019 10:51:40 -0700 Subject: [PATCH 02/22] Switch submodules to https --- .gitmodules | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 03507b25..20898374 100644 --- a/.gitmodules +++ b/.gitmodules @@ -42,7 +42,7 @@ url = https://github.com/ucb-bar/esp-tools.git [submodule "vlsi/hammer"] path = vlsi/hammer - url = git@github.com:ucb-bar/hammer.git + url = https://github.com/ucb-bar/hammer.git [submodule "vlsi/hammer-cad-plugins"] path = vlsi/hammer-cad-plugins - url = git@github.com:ucb-bar/hammer-cad-plugins + url = https://github.com/ucb-bar/hammer-cad-plugins From 87195152abe742f932e19185a0bd2efb40a9f1ea Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 13:24:32 -0700 Subject: [PATCH 03/22] added .git to end of hammer-cad-plugins --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 20898374..5bbbedd0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -45,4 +45,4 @@ url = https://github.com/ucb-bar/hammer.git [submodule "vlsi/hammer-cad-plugins"] path = vlsi/hammer-cad-plugins - url = https://github.com/ucb-bar/hammer-cad-plugins + url = https://github.com/ucb-bar/hammer-cad-plugins.git From 288ec15ba5d35ef17d1572709b19444d8ae3a916 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 24 Jul 2019 15:22:06 -0700 Subject: [PATCH 04/22] Fix run-binary-debug verbosity --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index f9d5896b..76baf09c 100644 --- a/common.mk +++ b/common.mk @@ -96,7 +96,7 @@ run-binary-fast: $(sim) # helper rules to run simulator with as much debug info as possible ######################################################################################### run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) run-fast: run-asm-tests-fast run-bmark-tests-fast From 89b312a8891a4df855d82d4accdfb0db20613d65 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 22:42:21 -0700 Subject: [PATCH 05/22] move boom integration to chipyard --- generators/boom | 2 +- .../example/src/main/scala/BoomConfigs.scala | 97 +++++++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 9 ++ .../example/src/main/scala/Configs.scala | 30 +++--- .../example/src/main/scala/TestHarness.scala | 48 ++++++++- generators/example/src/main/scala/Top.scala | 13 ++- variables.mk | 2 +- 7 files changed, 179 insertions(+), 22 deletions(-) create mode 100644 generators/example/src/main/scala/BoomConfigs.scala diff --git a/generators/boom b/generators/boom index 51bfc070..962e9467 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 51bfc070e8b4750f5401b5db235233421ab8deba +Subproject commit 962e94674ebd859d4798efe44cb6e404be9a5076 diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala new file mode 100644 index 00000000..e8044080 --- /dev/null +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -0,0 +1,97 @@ +//****************************************************************************** +// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). +// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. +//------------------------------------------------------------------------------ +// Author: Christopher Celio, Abraham Gonzalez, Ben Korpan, Jerry Zhao +//------------------------------------------------------------------------------ + +package example + +import chisel3._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.subsystem.{WithJtagDTM} + +import boom.common._ + +// --------------------- +// BOOM Configs +// --------------------- + +class SmallBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallBoomConfig) + +class MediumBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MediumBoomConfig) + +class LargeBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.LargeBoomConfig) + +class MegaBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MegaBoomConfig) + +class jtagSmallBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.SmallBoomConfig) + +class jtagMediumBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.MediumBoomConfig) + +class jtagLargeBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.LargeBoomConfig) + +class jtagMegaBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.MegaBoomConfig) + +class SmallDualBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallDualBoomConfig) + +class TracedSmallBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.TracedSmallBoomConfig) + +class SmallRV32UnifiedBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallRV32UnifiedBoomConfig) + +// -------------------------- +// BOOM + Rocket Configs +// -------------------------- + +class SmallBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallBoomAndRocketConfig) + +class MediumBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MediumBoomAndRocketConfig) + +class DualMediumBoomAndDualRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.DualMediumBoomAndDualRocketConfig) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 895fa86a..17fac94d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -58,6 +58,15 @@ class WithNormalBoomRocketTop extends Config((site, here, up) => { } }) +/** + * Class to specify a top level BOOM and/or Rocket system with DTM + */ +class WithDTMBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomRocketTopWithDTM()(p)).module) + } +}) + /** * Class to specify a top level BOOM and/or Rocket system with PWM */ diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index c6cfa7a5..c7e70dd2 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -77,11 +77,11 @@ class HwachaL2Config extends Config( class BaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.LargeBoomConfig) + new boom.common.LargeBoomConfig) class SmallBaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.SmallBoomConfig) + new boom.common.SmallBoomConfig) class DefaultBoomConfig extends Config( new WithNormalBoomRocketTop ++ @@ -132,7 +132,7 @@ class DualCoreBoomConfig extends Config( new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) @@ -142,14 +142,14 @@ class DualCoreSmallBoomConfig extends Config( new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) + new boom.common.SmallRV32UnifiedBoomConfig) class BoomL2Config extends Config( new WithInclusiveCache ++ @@ -161,22 +161,22 @@ class BoomL2Config extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -223,11 +223,11 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -237,12 +237,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config( new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket - new boom.system.WithRenumberHarts(rocketFirst = true) ++ + new boom.common.WithRenumberHarts(rocketFirst = true) ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -250,12 +250,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithRV32 ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index c59a081e..778fcc81 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -8,14 +8,19 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp +import freechips.rocketchip.devices.debug.{Debug} -// -------------------------- +// ------------------------------- // BOOM and/or Rocket Test Harness -// -------------------------- +// ------------------------------- case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] +case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]] -class BoomRocketTestHarness(implicit val p: Parameters) extends Module { +/** + * Test harness using TSI to bringup the system + */ +class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) @@ -24,6 +29,7 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module { override def desiredName = "TestHarness" val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() @@ -41,5 +47,41 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module { axi.w.bits := DontCare } }) + io.success := dut.connectSimSerial() } + +/** + * Test harness using the Debug Test Module (DTM) to bringup the system + */ +class TestHarnessWithDTM(implicit p: Parameters) extends Module +{ + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p) + + dut.reset := reset.asBool | dut.debug.ndreset + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + + Debug.connectDebug(dut.debug, clock, reset.asBool, io.success) +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index a3fa99f8..b861fdec 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -12,9 +12,9 @@ import testchipip._ import sifive.blocks.devices.gpio._ -// ------------------------------- +// ------------------------------------ // BOOM and/or Rocket Top Level Systems -// ------------------------------- +// ------------------------------------ class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem with HasNoDebug @@ -67,3 +67,12 @@ class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) extends BoomRocketTopModule(l) with HasPeripheryGPIOModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem +{ + override lazy val module = new BoomRocketTopWithDTMModule(this) +} + +class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l) diff --git a/variables.mk b/variables.mk index a0c6a9af..fa7bb494 100644 --- a/variables.mk +++ b/variables.mk @@ -29,7 +29,7 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= BoomRocketTestHarness + MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig From a8dbc391a15334050aa4b4f658343d8c192565f0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 22:55:00 -0700 Subject: [PATCH 06/22] remove boom variables | update ci --- .circleci/defaults.sh | 2 +- generators/boom | 2 +- variables.mk | 12 ------------ 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 25b365d8..cdccc3ba 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -38,7 +38,7 @@ declare -A mapping mapping["example"]="SUB_PROJECT=example" mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig" mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig" -mapping["boom"]="SUB_PROJECT=boom" +mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha" diff --git a/generators/boom b/generators/boom index 962e9467..3a06403d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 962e94674ebd859d4798efe44cb6e404be9a5076 +Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5 diff --git a/variables.mk b/variables.mk index fa7bb494..66eb0518 100644 --- a/variables.mk +++ b/variables.mk @@ -38,18 +38,6 @@ ifeq ($(SUB_PROJECT),example) TB ?= TestDriver TOP ?= BoomRocketTop endif -# for BOOM developers -ifeq ($(SUB_PROJECT),boom) - SBT_PROJECT ?= boom - MODEL ?= TestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= boom.system - CONFIG ?= LargeBoomConfig - CONFIG_PACKAGE ?= boom.system - GENERATOR_PACKAGE ?= boom.system - TB ?= TestDriver - TOP ?= BoomRocketSystem -endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT ?= rocketchip From 495e9d2668cfeb69075b0d4d023019cbec53e412 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 24 Jul 2019 23:19:18 -0700 Subject: [PATCH 07/22] Do not clobber LD_LIBRARY_PATH in env.sh --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index ac4316b7..15a615d3 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -138,7 +138,7 @@ cd $RDIR echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh echo "export RISCV=$RISCV" >> env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh -echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh +echo "export LD_LIBRARY_PATH=$RISCV/lib:\$LD_LIBRARY_PATH" >> env.sh echo "Toolchain Build Complete!" From 6156716876f521a43ef59f1eb78c6ae0fb066d58 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 25 Jul 2019 07:59:21 -0700 Subject: [PATCH 08/22] hammer docs outline --- docs/VLSI/HAMMER.rst | 35 ++++++++++++++++++++++++++++++++++- docs/VLSI/index.rst | 8 ++++---- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index a206fe93..ffd880be 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -1,7 +1,40 @@ -HAMMER +Core HAMMER ================================ `HAMMER `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. For more information, read the `HAMMER paper `__ and see the `GitHub repository `__. + +Actions +------- + +Actions are the top-level tasks Hammer is capable of executing (e.g. synthesis, place-and-route, etc.) + +Steps +------- + +Steps are the sub-components of actions that individually addressable in Hammer (e.g. placement in the place-and-route action). + +Hooks +------- + +Hooks are modifications to steps or actions that are programmaticly defined in a Hammer configuration. + +Tool Plugins +============ + +Hammer supports separatly managed plugins for different CAD tool vendors. + +Technology Plugins +================== + +Hammer supports separately managed plugins for different technologies. + + +Configuration +============= + +To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. + +You can see the current set of all avaialable Hammer APIs `here `. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 464d9828..259966d8 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -1,11 +1,11 @@ -VLSI Production +VLSI Flow ================================ -The Chipyard framework aim to provide wrappers to a general VLSI flow. -In particular, we aim to support the HAMMER flow. +The Chipyard framework aims to provide wrappers for a general VLSI flow. +In particular, we aim to support the HAMMER physical deisgn generator flow. .. toctree:: :maxdepth: 2 - :caption: VLSI Production: + :caption: VLSI Flow: HAMMER From 60f603e7c8d1dc223123d3140e1a697c8cf81728 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 25 Jul 2019 15:19:59 -0700 Subject: [PATCH 09/22] Safer LD_LIBRARY_PATH --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 15a615d3..e743afe4 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -138,7 +138,7 @@ cd $RDIR echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh echo "export RISCV=$RISCV" >> env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh -echo "export LD_LIBRARY_PATH=$RISCV/lib:\$LD_LIBRARY_PATH" >> env.sh +echo "export LD_LIBRARY_PATH=$RISCV/lib\${LD_LIBRARY_PATH:+":${LD_LIBRARY_PATH}"}" >> env.sh echo "Toolchain Build Complete!" From c6f4f36f07c17add3bd81c8257c435cba2c85054 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 26 Jul 2019 16:34:49 -0700 Subject: [PATCH 10/22] Switch to auto-generated hammer makefile fragment (#181) * Switch to auto-generated hammer makefile fragment * Add hammer_d_deps Co-Authored-By: John Wright --- vlsi/Makefile | 147 +++++++++++++++++++++++--------------------------- vlsi/hammer | 2 +- 2 files changed, 67 insertions(+), 82 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index fc0b4ac6..519d1448 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -14,109 +14,94 @@ sim_dir=$(abspath .) ######################################################################################### include $(base_dir)/variables.mk +######################################################################################### +# vlsi types and rules +######################################################################################### +sim_name ?= vcs # needed for GenerateSimFiles, but is unused +tech_name ?= +tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) +SMEMS_COMP ?= $(tech_dir)/sram-compiler.json +SMEMS_CACHE ?= $(tech_dir)/sram-cache.json +SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json +MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) +OBJ_DIR ?= $(vlsi_dir)/build +ENV_YML ?= $(vlsi_dir)/bwrc-env.yml +INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml +HAMMER_EXEC ?= ./example-vlsi + +######################################################################################### +# general rules +######################################################################################### +ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes) +extra_v_includes = $(build_dir)/EICG_wrapper.v + +.PHONY: default verilog +default: all + +all: drc lvs + +verilog: $(ALL_RTL) + ######################################################################################### # import other necessary rules and variables ######################################################################################### include $(base_dir)/common.mk ######################################################################################### -# vlsi types and rules +# srams ######################################################################################### +SRAM_GENERATOR_CONF = $(build_dir)/sram_generator-input.yml +SRAM_CONF=$(build_dir)/sram_generator-output.json -#sim_name is unused, but GenerateSimFiles expects it -sim_name ?= vcs -tech_name ?= -tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) -SMEMS_COMP ?= $(tech_dir)/sram-compiler.json -SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) -OBJ_DIR ?= $(vlsi_dir)/build -ENV_YML ?= $(vlsi_dir)/bwrc-env.yml -INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml -HAMMER_EXEC ?= ./example-vlsi +## SRAM Generator +.PHONY: sram_generator srams +srams: sram_generator +sram_generator: $(SRAM_CONF) -ROCKET_SRC_DIR=$(ROCKETCHIP_DIR)/src/main/resources/vsrc +# This should be built alongside $(SMEMS_FILE) +$(SMEMS_HAMMER): $(SMEMS_FILE) -ROCKET_SRCS = \ - $(ROCKET_SRC_DIR)/ClockDivider2.v \ - $(ROCKET_SRC_DIR)/ClockDivider3.v \ - $(ROCKET_SRC_DIR)/AsyncResetReg.v \ - $(ROCKET_SRC_DIR)/plusarg_reader.v \ - $(ROCKET_SRC_DIR)/EICG_wrapper.v \ +$(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER) + mkdir -p $(dir $@) + echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ + echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ -ALL_RTL = $(ROCKET_SRCS) $(TOP_FILE) $(TOP_SMEMS_FILE) +$(SRAM_CONF): $(SRAM_GENERATOR_CONF) + cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator + cd $(vlsi_dir) && cp output.json $@ -CLOCK_DOMAINS = $(build_dir)/$(long_name).domains +######################################################################################### +# synthesis input configuration +######################################################################################### +SYN_CONF = $(OBJ_DIR)/inputs.yml +GENERATED_CONFS = $(SYN_CONF) $(SRAM_CONF) -.PHONY: default -default: all - -all: drc lvs - - -###################################################### SYN ############################################################ - -SYNTH_CONF = $(OBJ_DIR)/inputs.yml - -$(SYNTH_CONF): +$(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes) mkdir -p $(dir $@) echo "synthesis.inputs:" > $@ echo " top_module: $(TOP)" >> $@ echo " input_files:" >> $@ - for x in $(ALL_RTL); do \ + for x in $(ALL_RTL) $(extra_v_includes) `cat $(sim_top_blackboxes)`; do \ echo ' - "'$$x'"' >> $@; \ done -GENERATED_CONFS=$(SYNTH_CONF) $(SRAM_CONF) +######################################################################################### +# AUTO BUILD FLOW +######################################################################################### -.PHONY: syn synthesis -syn: $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v -synthesis: syn +.PHONY: buildfile +buildfile: $(OBJ_DIR)/hammer.d +# Tip: Set HAMMER_D_DEPS to an empty string to avoid unnecessary RTL rebuilds +# TODO: make this dependency smarter so that we don't need this at all +HAMMER_D_DEPS ?= $(GENERATED_CONFS) +$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build -$(OBJ_DIR)/syn-rundir/$(TOP).mapped.v $(OBJ_DIR)/syn-rundir/syn-output.json: $(ENV_YML) $(INPUT_CONFS) $(GENERATED_CONFS) $(ALL_RTL) - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) syn - -$(OBJ_DIR)/par-input.json: $(OBJ_DIR)/syn-rundir/syn-output.json - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $<, -p $(x)) -o $@ syn_to_par - -###################################################### PAR ############################################################ - -.PHONY: par place-and-route -par: $(OBJ_DIR)/par-rundir/$(TOP).gds -place-and-route: par - -$(OBJ_DIR)/par-rundir/$(TOP).gds $(OBJ_DIR)/par-rundir/par-output.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) par - -$(OBJ_DIR)/drc-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_drc - -###################################################### DRC ############################################################ -# TODO unimplemented -.PHONY: drc -drc: $(OBJ_DIR)/drc-rundir/drc_results.db - -$(OBJ_DIR)/drc-rundir/drc_results.db: $(OBJ_DIR)/drc-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) drc - -###################################################### LVS ############################################################ -# TODO unimplemented -$(OBJ_DIR)/lvs-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_lvs - -.PHONY: lvs -lvs: $(OBJ_DIR)/lvs-rundir/lvs_results.rpt - -$(OBJ_DIR)/lvs-rundir/lvs_results.rpt: $(OBJ_DIR)/lvs-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) lvs +-include $(OBJ_DIR)/hammer.d +######################################################################################### +# general cleanup rule +######################################################################################### .PHONY: clean clean: - rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) generated-src + rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) diff --git a/vlsi/hammer b/vlsi/hammer index 873b2c1a..a27886fb 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 873b2c1af0a54cb339a19a7c8cf3a1e7905feb58 +Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 From 91107ce04370a97606557dd83429c294e9769244 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 29 Jul 2019 15:33:31 -0700 Subject: [PATCH 11/22] Ignore emacs temp files --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 8450e9b8..af37395a 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,8 @@ target *.stamp *.vcd *.swp +*# +*~ .idea .DS_Store env.sh From 7dc05e678fcf308e1171a413571c931322645fbb Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Tue, 30 Jul 2019 13:58:11 -0700 Subject: [PATCH 12/22] Bump firrtl, filter Emitted and Circuit annotations to save heap space (#183) --- tools/barstools | 2 +- tools/firrtl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/barstools b/tools/barstools index 82636b3f..e3c82270 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 82636b3ff43ecf6a0f0a7d46ebc2456b31e9703f +Subproject commit e3c822709be39090ea9dad74d55239d5fc560d25 diff --git a/tools/firrtl b/tools/firrtl index 99ae1d66..84a1c7b1 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 99ae1d6649f1731c5dec2098b10733735232b72c +Subproject commit 84a1c7b1f7311ce036cb7d3d5eb652466b87dce4 From c487ca2f66dcc512c9066f4255247f00e9f5dce5 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 31 Jul 2019 09:36:52 -0700 Subject: [PATCH 13/22] Coordinate Top and Harness generation (#168) * Coordinate Top and Harness generation * Bump barstools --- common.mk | 17 +++++++---------- tools/barstools | 2 +- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/common.mk b/common.mk index 76baf09c..2be99ffe 100644 --- a/common.mk +++ b/common.mk @@ -47,16 +47,13 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_files) # create verilog files rules and variables ######################################################################################### REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF) -HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) +HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF) -$(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(TOP_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" - grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_top_blackboxes) +TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes) +HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes) -# note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time -$(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" - grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) +$(TOP_TARGETS) $(HARNESS_TARGETS): $(FIRRTL_FILE) $(ANNO_FILE) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops @@ -70,7 +67,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) ######################################################################################## # remove duplicate files in blackbox/simfiles ######################################################################################## -$(sim_common_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_files) +$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes) awk '{print $1;}' $^ | sort -u > $@ ######################################################################################### @@ -96,7 +93,7 @@ run-binary-fast: $(sim) # helper rules to run simulator with as much debug info as possible ######################################################################################### run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) run-fast: run-asm-tests-fast run-bmark-tests-fast diff --git a/tools/barstools b/tools/barstools index e3c82270..26096e07 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e3c822709be39090ea9dad74d55239d5fc560d25 +Subproject commit 26096e07f6ce3e12b2114132c2859ef56fb0cfaf From a18d3ed92040b5bfac803216716fe10f12b84c3b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 29 Jul 2019 22:37:21 -0700 Subject: [PATCH 14/22] Remove commit-on-master check We decided this was a bad idea, and that submodules should just avoid rebase-commits. --- .circleci/config.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index db4eb614..1ae4a000 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -439,10 +439,20 @@ jobs: # Order and dependencies of jobs to run workflows: version: 2 + submodules-on-master: + jobs: + # Check to make sure submodule commits are on master branches + - commit-on-master-check + triggers: + - schedule: + cron: "0 0 * * *" + filters: + branches: + only: + - master + build-and-test-chipyard-integration: jobs: - # check to make sure commits are on master - - commit-on-master-check # Make the toolchains - install-riscv-toolchain From 6d8a6b2412fb3f45fef470b401275b721658c3c7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 1 Aug 2019 11:22:05 -0700 Subject: [PATCH 15/22] remove header from BoomConfigs.scala --- generators/example/src/main/scala/BoomConfigs.scala | 7 ------- 1 file changed, 7 deletions(-) diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala index e8044080..f328b902 100644 --- a/generators/example/src/main/scala/BoomConfigs.scala +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -1,10 +1,3 @@ -//****************************************************************************** -// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). -// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. -//------------------------------------------------------------------------------ -// Author: Christopher Celio, Abraham Gonzalez, Ben Korpan, Jerry Zhao -//------------------------------------------------------------------------------ - package example import chisel3._ From cd48271b5314d0605bea01223a3f97b091ef63b8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 1 Aug 2019 22:33:21 -0700 Subject: [PATCH 16/22] Added DTM docs | bumped BOOM --- docs/Advanced-Usage/DTM-Debugging.rst | 48 +++++++++++++++++++++++++++ docs/Advanced-Usage/index.rst | 1 + generators/boom | 2 +- 3 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 docs/Advanced-Usage/DTM-Debugging.rst diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst new file mode 100644 index 00000000..953e9cbd --- /dev/null +++ b/docs/Advanced-Usage/DTM-Debugging.rst @@ -0,0 +1,48 @@ +Debugging with DTM/JTAG +=============================== + +By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core. +Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation). +However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system. + +Creating a DTM/JTAG Config +------------------------------------------- + +First, a DTM config must be created for the system that you want to create. +This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG. + +.. code-block:: scala + + class DTMBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.SmallBoomConfig) + +In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM. +The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup). +The rest of the mixins specify the rest of the system (cores, accelerators, etc). + +Starting the DTM Simulation +------------------------------------------- + +After creating the config, call the ``make`` command like the following: + +.. code-block:: bash + + cd sims/verilator + # or + cd sims/vcs + + make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM + +In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system. +After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB! + +Debugging with JTAG +------------------------------------------------------- + +Please refer to the following resources on how to debug with JTAG. + +* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb +* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst index 62dd11aa..1f313e60 100644 --- a/docs/Advanced-Usage/index.rst +++ b/docs/Advanced-Usage/index.rst @@ -9,3 +9,4 @@ They expect you to know about Chisel, Parameters, Configs, etc. :caption: Getting Started: Heterogeneous-SoCs + DTM-Debugging diff --git a/generators/boom b/generators/boom index 3a06403d..609cf36e 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5 +Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554 From 3baad45dce3e4fc90b623bc035ace567725d751c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 2 Aug 2019 21:43:23 -0700 Subject: [PATCH 17/22] update boom to master --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 609cf36e..96616414 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554 +Subproject commit 96616414e17474c4196ddea00ce9ea41d52dc143 From 717c4658ffa22717431db543bf5fc40770aca5cf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 6 Aug 2019 10:44:31 -0700 Subject: [PATCH 18/22] update boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 96616414..4e9d496d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96616414e17474c4196ddea00ce9ea41d52dc143 +Subproject commit 4e9d496d3678cc5ae005669a448ae9e89f8ae847 From 34f76056effe17f939caf52a92a6b334899f09aa Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 6 Aug 2019 22:57:49 -0600 Subject: [PATCH 19/22] Update docs/Advanced-Usage/DTM-Debugging.rst Co-Authored-By: Jerry Zhao --- docs/Advanced-Usage/DTM-Debugging.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst index 953e9cbd..bf033fec 100644 --- a/docs/Advanced-Usage/DTM-Debugging.rst +++ b/docs/Advanced-Usage/DTM-Debugging.rst @@ -3,6 +3,8 @@ Debugging with DTM/JTAG By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core. Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation). +TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM +executes a small loop of code to write the test binary byte-wise into memory. However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system. Creating a DTM/JTAG Config From 9844fcf43bcfc3590891971934ebdfcf29bad00d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 6 Aug 2019 22:16:46 -0700 Subject: [PATCH 20/22] re-add testsuites to compile --- .../example/src/main/scala/Generator.scala | 2 - .../example/src/main/scala/TestSuites.scala | 142 ++++++++++++++++++ 2 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 generators/example/src/main/scala/TestSuites.scala diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index 92658038..34f16e4e 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -5,8 +5,6 @@ import chisel3._ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{GeneratorApp} -import boom.system.{BoomTilesKey, TestSuiteHelper} - object Generator extends GeneratorApp { // add unique test suites override def addTestSuites { diff --git a/generators/example/src/main/scala/TestSuites.scala b/generators/example/src/main/scala/TestSuites.scala new file mode 100644 index 00000000..11425bdb --- /dev/null +++ b/generators/example/src/main/scala/TestSuites.scala @@ -0,0 +1,142 @@ +package example + +import scala.collection.mutable.{LinkedHashSet} + +import freechips.rocketchip.subsystem.{RocketTilesKey} +import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.util.{GeneratorApp} +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} + +import boom.system.{BoomTilesKey} + +/** + * A set of pre-chosen regression tests + */ +object RegressionTestSuites +{ + val rv64RegrTestNames = LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + "rv64mi-p-breakpoint", + "rv64uc-v-rvc", + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") +} + +/** + * Helper functions to add BOOM or Rocket tests + */ +object TestSuiteHelper +{ + import freechips.rocketchip.system.DefaultTestSuites._ + import RegressionTestSuites._ + + /** + * Add BOOM tests (asm, bmark, regression) + */ + def addBoomTestSuites(implicit p: Parameters) = { + val xlen = p(XLen) + p(BoomTilesKey).find(_.hartId == 0).map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) { + TestGeneration.addSuites(env.map(rv32ud)) + } + } else if (cfg.fLen >= 64) { + TestGeneration.addSuites(env.map(rv64ud)) + TestGeneration.addSuites(env.map(rv64uf)) + TestGeneration.addSuite(rv32udBenchmarks) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) { + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + } else { + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites(rvu.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + + /** + * Add Rocket tests (asm, bmark, regression) + */ + def addRocketTestSuites(implicit p: Parameters) = { + val xlen = p(XLen) + p(RocketTilesKey).find(_.hartId == 0).map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } +} From 80b6976be9beb13329cbd9bd5792ee00bd70cd63 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 8 Aug 2019 08:01:24 -0700 Subject: [PATCH 21/22] Add start of tool-plugin section. --- docs/VLSI/HAMMER.rst | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index ffd880be..162b703c 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -25,6 +25,26 @@ Tool Plugins ============ Hammer supports separatly managed plugins for different CAD tool vendors. +The types of tools(in there hammer names) supported currently include: + +* synthesis +* par +* drc +* lvs +* sram_generator +* pcb + +In order to configure your tool plugin of choice you will need to set several configuration variables. +First you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. +For example ``vlsi.core.par_tool: "innovus"``. +You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core._tool_path``. +This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifing the default values for any tool specific variables. +In addition you can also customize the version of the tools you use by setting ``..version`` to a tool specific string. +Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool. + +The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support. +This class should be a subclass of ``HammerTool``, which will be a subclass of ``HammerTool``. + Technology Plugins ================== @@ -37,4 +57,4 @@ Configuration To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. -You can see the current set of all avaialable Hammer APIs `here `. +You can see the current set of all avaialable Hammer APIs `here `__. From 9538257be14e421d171c5e35e8d262f12cc94ec9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Aug 2019 11:19:57 -0700 Subject: [PATCH 22/22] grammer + spell check --- docs/VLSI/HAMMER.rst | 16 +++++++--------- docs/VLSI/index.rst | 2 +- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index 162b703c..c0c77824 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -19,13 +19,13 @@ Steps are the sub-components of actions that individually addressable in Hammer Hooks ------- -Hooks are modifications to steps or actions that are programmaticly defined in a Hammer configuration. +Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration. Tool Plugins ============ -Hammer supports separatly managed plugins for different CAD tool vendors. -The types of tools(in there hammer names) supported currently include: +Hammer supports separately managed plugins for different CAD tool vendors. +The types of tools (in there hammer names) supported currently include: * synthesis * par @@ -34,27 +34,25 @@ The types of tools(in there hammer names) supported currently include: * sram_generator * pcb -In order to configure your tool plugin of choice you will need to set several configuration variables. -First you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. +In order to configure your tool plugin of choice, you will need to set several configuration variables. +First, you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. For example ``vlsi.core.par_tool: "innovus"``. You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core._tool_path``. -This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifing the default values for any tool specific variables. +This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifying the default values for any tool specific variables. In addition you can also customize the version of the tools you use by setting ``..version`` to a tool specific string. Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool. The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support. This class should be a subclass of ``HammerTool``, which will be a subclass of ``HammerTool``. - Technology Plugins ================== Hammer supports separately managed plugins for different technologies. - Configuration ============= To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. -You can see the current set of all avaialable Hammer APIs `here `__. +You can see the current set of all available Hammer APIs `here `__. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 259966d8..f8bdb7a8 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -2,7 +2,7 @@ VLSI Flow ================================ The Chipyard framework aims to provide wrappers for a general VLSI flow. -In particular, we aim to support the HAMMER physical deisgn generator flow. +In particular, we aim to support the HAMMER physical design generator flow. .. toctree:: :maxdepth: 2