From d28077ff0b71939a501dafc74e7ec45039951df6 Mon Sep 17 00:00:00 2001
From: Harrison Liew <harrisonliew@gmail.com>
Date: Mon, 2 Sep 2019 16:59:14 -0700
Subject: [PATCH] updated DCO collateral

---
 vlsi/README.md                                |  17 ++-
 vlsi/example.yml                              |  20 ++-
 vlsi/extra_libraries/dco/ExampleDCO.gds       | Bin 0 -> 10240 bytes
 .../dco/{dco.lef => ExampleDCO.lef}           | 100 ++++++------
 .../dco/ExampleDCO_PVT_0P63V_100C.lib         | 142 ++++++++++++++++++
 .../dco/ExampleDCO_PVT_0P77V_0C.lib           | 142 ++++++++++++++++++
 vlsi/extra_libraries/dco/dco.gds              | Bin 10240 -> 0 bytes
 7 files changed, 359 insertions(+), 62 deletions(-)
 create mode 100644 vlsi/extra_libraries/dco/ExampleDCO.gds
 rename vlsi/extra_libraries/dco/{dco.lef => ExampleDCO.lef} (76%)
 create mode 100644 vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib
 create mode 100644 vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib
 delete mode 100644 vlsi/extra_libraries/dco/dco.gds

diff --git a/vlsi/README.md b/vlsi/README.md
index 12cb6fd9..29fd2bc7 100644
--- a/vlsi/README.md
+++ b/vlsi/README.md
@@ -1,3 +1,4 @@
+# HAMMER VLSI flow
 This is the starting point for a vlsi flow from this repository.
 
 This flow will not work without the necessary CAD and technology plugins for HAMMER.
@@ -5,7 +6,7 @@ This flow will not work without the necessary CAD and technology plugins for HAM
 If you are a UCB-affiliate, you may be able to acquire access to the tool & tech plugins.
 
 # Initial Setup Instructions (For all technologies)
-Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the included technology 'asap7' is already included and will not submodule a tech plugin.
+Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the technologies `asap7` and `saed32` are already included and will not submodule a tech plugin.
 ```shell
 ./scripts/init-vlsi.sh TECH_NAME
 ```
@@ -13,15 +14,16 @@ Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_V
 An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment.
 
 # Example design
-In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system:
+## Building the design
+In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system:
 ```shell
 export MACROCOMPILER_MODE=' --mode synflops'
 export CONFIG=Sha3RocketConfig
-export TOP=Sha3AccelwBB
 make buildfile
 ```
 Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead.
 
+## Using HAMMER
 HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself.
 
 We start by pulling the HAMMER environment into the shell:
@@ -33,10 +35,15 @@ source $HAMMER_HOME/sourceme.sh
 
 The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks.
 
-In order to install the process, edit the keys `vlsi.technology.asap7.tarball_dir` if you already have the ASAP7 tarball downloaded and `vlsi.technology.asap7.install_dir` if you have already extracted it. If omitted, Hammer will automatically download and extract the tarballs into the `build/asap7-tech-cache` directory when you first run synthesis.
+In order to install the process, download (and optionally extract) the ASAP7 PDK tarball. Then, edit the key `vlsi.technology.asap7.tarball_dir` if you want Hammer to extract for you or `vlsi.technology.asap7.install_dir` if you have already extracted it.
 
-To synthesize a design:
+To synthesize the just the SHA-3 accelerator with the hard macro we have to change the physical top module (this step is not necessary if you are pushing the entire Rocket-chip through the VLSI flow):
+```shell
+export TOP=Sha3AccelwBB
+rm build/inputs.yml
+```
 
+Then, to run synthesis:
 ```shell
 make syn
 ```
diff --git a/vlsi/example.yml b/vlsi/example.yml
index d4251ad2..1c92731e 100644
--- a/vlsi/example.yml
+++ b/vlsi/example.yml
@@ -82,12 +82,15 @@ vlsi.inputs.pin.assignments: [
 ]
 
 # Paths to extra libraries
-vlsi.technology.extra_libraries_meta: "append"
+vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
 vlsi.technology.extra_libraries:
   - library:
-      nldm liberty file: "extra_libraries/dco/dco_SS.lib"
-      lef file: "extra_libraries/dco/dco.lef"
-      gds file: "extra_libraries/dco/dco.gds"
+      nldm liberty file_deepsubst_meta: "local"
+      nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib"
+      lef file_deepsubst_meta: "local"
+      lef file: "extra_libraries/dco/ExampleDCO.lef"
+      gds file_deepsubst_meta: "local"
+      gds file: "extra_libraries/dco/ExampleDCO.gds"
       corner:
         nmos: "slow"
         pmos: "slow"
@@ -96,9 +99,12 @@ vlsi.technology.extra_libraries:
         VDD: "0.63 V"
         GND: "0 V"
   - library:
-      nldm liberty file: "extra_libraries/dco/dco_FF.lib"
-      lef file: "extra_libraries/dco/dco.lef"
-      gds file: "extra_libraries/dco/dco.gds"
+      nldm liberty file_deepsubst_meta: "local"
+      nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib"
+      lef file_deepsubst_meta: "local"
+      lef file: "extra_libraries/dco/ExampleDCO.lef"
+      gds file_deepsubst_meta: "local"
+      gds file: "extra_libraries/dco/ExampleDCO.gds"
       corner:
         nmos: "fast"
         pmos: "fast"
diff --git a/vlsi/extra_libraries/dco/ExampleDCO.gds b/vlsi/extra_libraries/dco/ExampleDCO.gds
new file mode 100644
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diff --git a/vlsi/extra_libraries/dco/dco.lef b/vlsi/extra_libraries/dco/ExampleDCO.lef
similarity index 76%
rename from vlsi/extra_libraries/dco/dco.lef
rename to vlsi/extra_libraries/dco/ExampleDCO.lef
index 24a878f9..47c6808d 100644
--- a/vlsi/extra_libraries/dco/dco.lef
+++ b/vlsi/extra_libraries/dco/ExampleDCO.lef
@@ -2,19 +2,19 @@ VERSION 5.6 ;
 BUSBITCHARS "[]" ;
 DIVIDERCHAR "/" ;
 
-MACRO dco-layout
+MACRO ExampleDCO
   CLASS CORE ;
   ORIGIN 0 0 ;
-  FOREIGN dco-layout 0 0 ;
-  SIZE 32 BY 32 ;
+  FOREIGN ExampleDCO 0 0 ;
+  SIZE 32.001 BY 32 ;
   SYMMETRY X Y ;
-  SITE CoreSite ;
+  SITE coreSite ;
   PIN VDD
     DIRECTION INOUT ;
     USE POWER ;
     PORT
       LAYER M9 ;
-        RECT 8.42 31 8.58 32 ;
+        RECT 8.24 31 8.4 32 ;
     END
   END VDD
   PIN VSS
@@ -22,7 +22,7 @@ MACRO dco-layout
     USE GROUND ;
     PORT
       LAYER M9 ;
-        RECT 23.432 31 23.592 32 ;
+        RECT 23.28 31 23.44 32 ;
     END
   END VSS
   PIN col_sel_b[13]
@@ -30,7 +30,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 30.202 1.00 30.298 ;
+        RECT 0 28.32 1 28.416 ;
     END
   END col_sel_b[13]
   PIN col_sel_b[11]
@@ -38,7 +38,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 28.702 1.00 28.798 ;
+        RECT 0 26.912 1 27.008 ;
     END
   END col_sel_b[11]
   PIN col_sel_b[5]
@@ -46,7 +46,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 24.202 1.00 24.298 ;
+        RECT 0 22.688 1 22.784 ;
     END
   END col_sel_b[5]
   PIN col_sel_b[12]
@@ -54,7 +54,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 29.452 1.00 29.548 ;
+        RECT 0 27.616 1 27.712 ;
     END
   END col_sel_b[12]
   PIN col_sel_b[10]
@@ -62,7 +62,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 27.952 1.00 28.048 ;
+        RECT 0 26.208 1 26.304 ;
     END
   END col_sel_b[10]
   PIN col_sel_b[9]
@@ -70,7 +70,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 27.202 1.00 27.298 ;
+        RECT 0 25.504 1 25.6 ;
     END
   END col_sel_b[9]
   PIN col_sel_b[8]
@@ -78,7 +78,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 26.452 1.00 26.548 ;
+        RECT 0 24.8 1 24.896 ;
     END
   END col_sel_b[8]
   PIN col_sel_b[7]
@@ -86,7 +86,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 25.702 1.00 25.798 ;
+        RECT 0 24.096 1 24.192 ;
     END
   END col_sel_b[7]
   PIN col_sel_b[6]
@@ -94,7 +94,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 24.952 1.00 25.048 ;
+        RECT 0 23.392 1 23.488 ;
     END
   END col_sel_b[6]
   PIN col_sel_b[4]
@@ -102,7 +102,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 23.452 1.00 23.548 ;
+        RECT 0 21.984 1 22.08 ;
     END
   END col_sel_b[4]
   PIN col_sel_b[3]
@@ -110,7 +110,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 22.702 1.00 22.798 ;
+        RECT 0 21.28 1 21.376 ;
     END
   END col_sel_b[3]
   PIN col_sel_b[2]
@@ -118,7 +118,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 21.952 1.00 22.048 ;
+        RECT 0 20.576 1 20.672 ;
     END
   END col_sel_b[2]
   PIN col_sel_b[1]
@@ -126,7 +126,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 21.202 1.00 21.298 ;
+        RECT 0 19.872 1 19.968 ;
     END
   END col_sel_b[1]
   PIN col_sel_b[0]
@@ -134,7 +134,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 20.452 1.00 20.548 ;
+        RECT 0 19.168 1 19.264 ;
     END
   END col_sel_b[0]
   PIN row_sel_b[14]
@@ -142,7 +142,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 18.952 1.00 19.048 ;
+        RECT 0 17.76 1 17.856 ;
     END
   END row_sel_b[14]
   PIN row_sel_b[13]
@@ -150,7 +150,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 18.202 1.00 18.298 ;
+        RECT 0 17.056 1 17.152 ;
     END
   END row_sel_b[13]
   PIN row_sel_b[12]
@@ -158,7 +158,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 17.452 1.00 17.548 ;
+        RECT 0 16.352 1 16.448 ;
     END
   END row_sel_b[12]
   PIN row_sel_b[11]
@@ -166,7 +166,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 16.702 1.00 16.798 ;
+        RECT 0 15.648 1 15.744 ;
     END
   END row_sel_b[11]
   PIN row_sel_b[10]
@@ -174,7 +174,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 15.952 1.00 16.048 ;
+        RECT 0 14.944 1 15.04 ;
     END
   END row_sel_b[10]
   PIN row_sel_b[9]
@@ -182,7 +182,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 15.202 1.00 15.298 ;
+        RECT 0 14.24 1 14.336 ;
     END
   END row_sel_b[9]
   PIN row_sel_b[8]
@@ -190,7 +190,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 14.452 1.00 14.548 ;
+        RECT 0 13.536 1 13.632 ;
     END
   END row_sel_b[8]
   PIN row_sel_b[7]
@@ -198,7 +198,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 13.702 1.00 13.798 ;
+        RECT 0 12.832 1 12.928 ;
     END
   END row_sel_b[7]
   PIN row_sel_b[6]
@@ -206,7 +206,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 12.952 1.00 13.048 ;
+        RECT 0 12.128 1 12.224 ;
     END
   END row_sel_b[6]
   PIN row_sel_b[5]
@@ -214,7 +214,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 12.202 1.00 12.298 ;
+        RECT 0 11.424 1 11.52 ;
     END
   END row_sel_b[5]
   PIN row_sel_b[4]
@@ -222,7 +222,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 11.452 1.00 11.548 ;
+        RECT 0 10.72 1 10.816 ;
     END
   END row_sel_b[4]
   PIN row_sel_b[3]
@@ -230,7 +230,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 10.702 1.00 10.798 ;
+        RECT 0 10.016 1 10.112 ;
     END
   END row_sel_b[3]
   PIN row_sel_b[2]
@@ -238,7 +238,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 9.952 1.00 10.048 ;
+        RECT 0 9.312 1 9.408 ;
     END
   END row_sel_b[2]
   PIN row_sel_b[1]
@@ -246,7 +246,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 9.202 1.00 9.298 ;
+        RECT 0 8.608 1 8.704 ;
     END
   END row_sel_b[1]
   PIN row_sel_b[0]
@@ -254,7 +254,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 8.452 1.00 8.548 ;
+        RECT 0 7.904 1 8 ;
     END
   END row_sel_b[0]
   PIN code_regulator[7]
@@ -262,7 +262,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 7.702 1.00 7.798 ;
+        RECT 0 7.2 1 7.296 ;
     END
   END code_regulator[7]
   PIN code_regulator[6]
@@ -270,7 +270,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 6.952 1.00 7.048 ;
+        RECT 0 6.496 1 6.592 ;
     END
   END code_regulator[6]
   PIN code_regulator[5]
@@ -278,7 +278,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 6.202 1.00 6.298 ;
+        RECT 0 5.792 1 5.888 ;
     END
   END code_regulator[5]
   PIN code_regulator[4]
@@ -286,7 +286,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 5.452 1.00 5.548 ;
+        RECT 0 5.088 1 5.184 ;
     END
   END code_regulator[4]
   PIN code_regulator[3]
@@ -294,7 +294,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 4.702 1.00 4.798 ;
+        RECT 0 4.384 1 4.48 ;
     END
   END code_regulator[3]
   PIN code_regulator[2]
@@ -302,7 +302,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 3.952 1.00 4.048 ;
+        RECT 0 3.68 1 3.776 ;
     END
   END code_regulator[2]
   PIN code_regulator[1]
@@ -310,7 +310,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 3.202 1.00 3.298 ;
+        RECT 0 2.976 1 3.072 ;
     END
   END code_regulator[1]
   PIN code_regulator[0]
@@ -318,7 +318,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 2.452 1.00 2.548 ;
+        RECT 0 2.272 1 2.368 ;
     END
   END code_regulator[0]
   PIN row_sel_b[15]
@@ -326,7 +326,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0.002 19.702 1.002 19.798 ;
+        RECT 0 18.464 1 18.56 ;
     END
   END row_sel_b[15]
   PIN dither
@@ -334,7 +334,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 0 1.702 1.00 1.798 ;
+        RECT 0 1.568 1 1.664 ;
     END
   END dither
   PIN sleep_b
@@ -342,7 +342,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M5 ;
-        RECT 2.466 0 2.562 1 ;
+        RECT 2.448 0 2.544 1 ;
     END
   END sleep_b
   PIN clock
@@ -350,7 +350,7 @@ MACRO dco-layout
     USE SIGNAL ;
     PORT
       LAYER M4 ;
-        RECT 31 17.452 32 17.548 ;
+        RECT 31 17.716 32 17.812 ;
     END
   END clock
   OBS
@@ -362,15 +362,15 @@ MACRO dco-layout
       RECT 1 1 31 31 ;
     LAYER M4 ;
       RECT 1 1 31 31 ;
-    LAYER M5 ;
-      RECT 1 1 31 31 ;
     LAYER M6 ;
       RECT 1 1 31 31 ;
     LAYER M7 ;
       RECT 1 1 31 31 ;
     LAYER M8 ;
       RECT 1 1 31 31 ;
+    LAYER M9 ;
+      RECT 1 1 31 31 ;
   END
-END dco-layout
+END ExampleDCO
 
 END LIBRARY
diff --git a/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib b/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib
new file mode 100644
index 00000000..9bf81dc4
--- /dev/null
+++ b/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib
@@ -0,0 +1,142 @@
+library (ExampleDCO_PVT_0P63V_100C) {
+    technology (cmos);
+    date : "Mon Sep  2 16:01:59 2019";
+    comment : "Generated by dotlibber.py";
+    revision : 0;
+    delay_model : table_lookup;
+    simulation : true;
+    capacitive_load_unit (1,pf);
+    voltage_unit : "1V";
+    current_unit : "1mA";
+    time_unit : "1ns";
+    pulling_resistance_unit : "1kohm";
+    nom_process : 1;
+    nom_temperature : 100;
+    nom_voltage : 0.630000;
+    voltage_map(VDD, 0.630000);
+    voltage_map(VSS, 0.000000);
+    operating_conditions("PVT_0P63V_100C") {
+        process : 1;
+        temperature : 100;
+        voltage : 0.630000;
+    }
+    default_operating_conditions : PVT_0P63V_100C;
+    lu_table_template (constraint_template_3x3) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1 ("0.0002, 0.0004, 0.0006");
+        index_2 ("0.0002, 0.0004, 0.0006");
+    }
+    lu_table_template (delay_template_8x8) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008");
+        index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
+    }
+
+
+    type (bus_13_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 14 ;
+        bit_from : 13 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+
+    type (bus_15_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 16 ;
+        bit_from : 15 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+
+    type (bus_7_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8 ;
+        bit_from : 7 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    cell (ExampleDCO) {
+        dont_use : true;
+        dont_touch : true;
+        is_macro_cell : true;
+
+        pg_pin (VDD) {
+            pg_type : primary_power;
+            voltage_name : VDD;
+        }
+
+        pg_pin (VSS) {
+            pg_type : primary_ground;
+            voltage_name : VSS;
+        }
+
+        pin (clock) {
+            direction : output;
+            clock : true;
+            max_capacitance : 0.02;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+
+        bus ( col_sel_b ) {
+            bus_type : bus_13_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+
+            pin ( col_sel_b[13:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        bus ( row_sel_b ) {
+            bus_type : bus_15_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+
+            pin ( row_sel_b[15:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        bus ( code_regulator ) {
+            bus_type : bus_7_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+
+            pin ( code_regulator[7:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        pin (dither) {
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+
+        pin (sleep_b) {
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+    }
+
+}
diff --git a/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib b/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib
new file mode 100644
index 00000000..f0b39fc4
--- /dev/null
+++ b/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib
@@ -0,0 +1,142 @@
+library (ExampleDCO_PVT_0P77V_0C) {
+    technology (cmos);
+    date : "Mon Sep  2 16:01:59 2019";
+    comment : "Generated by dotlibber.py";
+    revision : 0;
+    delay_model : table_lookup;
+    simulation : true;
+    capacitive_load_unit (1,pf);
+    voltage_unit : "1V";
+    current_unit : "1mA";
+    time_unit : "1ns";
+    pulling_resistance_unit : "1kohm";
+    nom_process : 1;
+    nom_temperature : 0;
+    nom_voltage : 0.770000;
+    voltage_map(VDD, 0.770000);
+    voltage_map(VSS, 0.000000);
+    operating_conditions("PVT_0P77V_0C") {
+        process : 1;
+        temperature : 0;
+        voltage : 0.770000;
+    }
+    default_operating_conditions : PVT_0P77V_0C;
+    lu_table_template (constraint_template_3x3) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1 ("0.0001, 0.0002, 0.0003");
+        index_2 ("0.0001, 0.0002, 0.0003");
+    }
+    lu_table_template (delay_template_8x8) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1 ("0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001");
+        index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
+    }
+
+
+    type (bus_13_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 14 ;
+        bit_from : 13 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+
+    type (bus_15_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 16 ;
+        bit_from : 15 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+
+    type (bus_7_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8 ;
+        bit_from : 7 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    cell (ExampleDCO) {
+        dont_use : true;
+        dont_touch : true;
+        is_macro_cell : true;
+
+        pg_pin (VDD) {
+            pg_type : primary_power;
+            voltage_name : VDD;
+        }
+
+        pg_pin (VSS) {
+            pg_type : primary_ground;
+            voltage_name : VSS;
+        }
+
+        pin (clock) {
+            direction : output;
+            clock : true;
+            max_capacitance : 0.02;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+
+        bus ( col_sel_b ) {
+            bus_type : bus_13_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+
+            pin ( col_sel_b[13:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        bus ( row_sel_b ) {
+            bus_type : bus_15_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+
+            pin ( row_sel_b[15:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        bus ( code_regulator ) {
+            bus_type : bus_7_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+
+            pin ( code_regulator[7:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        pin (dither) {
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+
+        pin (sleep_b) {
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.039999999999999994;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+    }
+
+}
diff --git a/vlsi/extra_libraries/dco/dco.gds b/vlsi/extra_libraries/dco/dco.gds
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