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Bump Rocketchip to June 2020 for Tile changes

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This commit is contained in:
Jerry Zhao
2020-06-18 10:48:32 -07:00
parent 781d644ea8
commit d245df9133
21 changed files with 375 additions and 536 deletions
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114
generators/tracegen/src/main/scala/Tile.scala
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@@ -3,36 +3,17 @@ package tracegen
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing}
import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus}
import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF, HellaCacheExceptions, HellaCacheReq, HellaCacheIO}
import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing, ClockCrossingType}
import freechips.rocketchip.groundtest._
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate, TileKey}
import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode}
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.subsystem._
import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters)
extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) {
val dcache = params.dcache.map { dc => LazyModule(
if (dc.nMSHRs == 0) new DCache(hartId, crossing)
else new NonBlockingDCache(hartId))
}.get
val intInwardNode: IntInwardNode = IntIdentityNode()
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val ceaseNode: IntOutwardNode = IntIdentityNode()
val haltNode: IntOutwardNode = IntIdentityNode()
val wfiNode: IntOutwardNode = IntIdentityNode()
val masterNode = visibilityNode
masterNode := dcache.node
override lazy val module = new TraceGenTileModuleImp(this)
}
class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
with MemoryOpConstants {
@@ -179,32 +160,58 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
}
class BoomTraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters)
extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) {
case class BoomTraceGenTileAttachParams(
tileParams: BoomTraceGenParams,
crossingParams: TileCrossingParamsLike
) extends CanAttachTile {
type TileType = BoomTraceGenTile
val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams)
}
case class BoomTraceGenParams(
wordBits: Int,
addrBits: Int,
addrBag: List[BigInt],
maxRequests: Int,
memStart: BigInt,
numGens: Int,
dcache: Option[DCacheParams] = Some(DCacheParams()),
hartId: Int = 0
) extends InstantiableTileParams[BoomTraceGenTile] with GroundTestTileParams
{
def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = {
new BoomTraceGenTile(this, crossing, lookup)
}
val beuAddr = None
val blockerCtrlAddr = None
val name = None
val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId)
}
class BoomTraceGenTile private(
val params: BoomTraceGenParams,
crossing: ClockCrossingType,
lookup: LookupByHartIdImpl,
q: Parameters) extends GroundTestTile(params, crossing, lookup, q)
{
def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
dcache=params.dcache,
core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false))))
val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params))
val intInwardNode: IntInwardNode = IntIdentityNode()
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val ceaseNode: IntOutwardNode = IntIdentityNode()
val haltNode: IntOutwardNode = IntIdentityNode()
val wfiNode: IntOutwardNode = IntIdentityNode()
val masterNode = visibilityNode
masterNode := dcache.node
val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode())
override lazy val module = new BoomTraceGenTileModuleImp(this)
}
class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
extends BaseTileModuleImp(outer){
extends GroundTestTileModuleImp(outer){
val status = IO(new GroundTestStatus)
val tracegen = Module(new TraceGenerator(outer.params))
val tracegen = Module(new TraceGenerator(outer.params.traceParams))
tracegen.io.hartid := constants.hartid
val ptw = Module(new DummyPTW(1))
@@ -219,31 +226,14 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
lsu.io.hellacache := DontCare
lsu.io.hellacache.req.valid := false.B
status.finished := tracegen.io.finished
status.timeout.valid := tracegen.io.timeout
status.timeout.bits := 0.U
status.error.valid := false.B
}
outer.reportCease(Some(tracegen.io.finished))
outer.reportHalt(Some(tracegen.io.timeout))
outer.reportWFI(None)
class TraceGenTileModuleImp(outer: TraceGenTile)
extends BaseTileModuleImp(outer) {
val status = IO(new GroundTestStatus)
val halt_and_catch_fire = None
val ptw = Module(new DummyPTW(1))
ptw.io.requestors.head <> outer.dcache.module.io.ptw
val tracegen = Module(new TraceGenerator(outer.params))
tracegen.io.hartid := constants.hartid
val dcacheIF = Module(new SimpleHellaCacheIF())
dcacheIF.io.requestor <> tracegen.io.mem
outer.dcache.module.io.cpu <> dcacheIF.io.cache
status.finished := tracegen.io.finished
status.timeout.valid := tracegen.io.timeout
status.timeout.bits := 0.U
status.error.valid := false.B
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out")
}