Bump Rocketchip to June 2020 for Tile changes
This commit is contained in:
Jerry Zhao
@@ -3,87 +3,126 @@ package tracegen
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import chisel3._
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import chisel3.util.log2Ceil
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import freechips.rocketchip.config.{Config, Parameters}
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import freechips.rocketchip.groundtest.{TraceGenParams}
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import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey}
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import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.system.BaseConfig
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import freechips.rocketchip.rocket.DCacheParams
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import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
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import scala.math.{max, min}
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class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val nSets = dcp.nSets
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val nWays = dcp.nWays
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = min(2, site(SystemBusKey).blockBeats)
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val beatBytes = site(SystemBusKey).beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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class WithTraceGen(
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n: Int = 2,
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overrideIdOffset: Option[Int] = None,
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overrideMemOffset: Option[BigInt] = None)(
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params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
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nReqs: Int = 8192
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) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => {
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val prev = up(TilesLocated(InSubsystem), site)
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val idOffset = overrideIdOffset.getOrElse(prev.size)
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val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
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params.zipWithIndex.map { case (dcp, i) =>
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TraceGenTileAttachParams(
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tileParams = TraceGenParams(
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hartId = i + idOffset,
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val nSets = dcp.nSets
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val nWays = dcp.nWays
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = min(2, site(SystemBusKey).blockBeats)
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val beatBytes = site(SystemBusKey).beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = memOffset,
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numGens = params.size),
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crossingParams = RocketCrossingParams()
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)
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} ++ prev
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}
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case MaxHartIdBits => log2Ceil(params.size + up(BoomTraceGenKey, site).length) max 1
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})
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class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case BoomTraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val nSets = dcp.nSets
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val nWays = dcp.nWays
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = min(2, site(SystemBusKey).blockBeats)
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val beatBytes = site(SystemBusKey).beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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class WithBoomTraceGen(
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n: Int = 2,
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overrideIdOffset: Option[Int] = None,
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overrideMemOffset: Option[BigInt] = None)(
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params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
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nReqs: Int = 8192
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) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => {
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val prev = up(TilesLocated(InSubsystem), site)
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val idOffset = overrideIdOffset.getOrElse(prev.size)
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val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
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params.zipWithIndex.map { case (dcp, i) =>
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BoomTraceGenTileAttachParams(
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tileParams = BoomTraceGenParams(
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hartId = i + idOffset,
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val nSets = dcp.nSets
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val nWays = dcp.nWays
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val blockOffset = site(SystemBusKey).blockOffset
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val nBeats = site(SystemBusKey).blockBeats
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List.tabulate(nWays) { i =>
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Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
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}.flatten
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},
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maxRequests = nReqs,
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memStart = memOffset,
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numGens = params.size),
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crossingParams = RocketCrossingParams()
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)
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} ++ prev
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}
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case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1
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})
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class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
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extends Config((site, here, up) => {
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case TraceGenKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val sbp = site(SystemBusKey)
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val l2p = site(InclusiveCacheKey)
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val nSets = max(l2p.sets, dcp.nSets)
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val nWays = max(l2p.ways, dcp.nWays)
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val blockOffset = sbp.blockOffset
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val nBeats = min(2, sbp.blockBeats)
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val beatBytes = sbp.beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).get.master.base,
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numGens = params.size)
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}
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case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
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})
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class WithL2TraceGen(
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n: Int = 2,
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overrideIdOffset: Option[Int] = None,
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overrideMemOffset: Option[BigInt] = None)(
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params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
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nReqs: Int = 8192
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) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => {
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val prev = up(TilesLocated(InSubsystem), site)
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val idOffset = overrideIdOffset.getOrElse(prev.size)
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val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
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params.zipWithIndex.map { case (dcp, i) =>
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TraceGenTileAttachParams(
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tileParams = TraceGenParams(
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hartId = i + idOffset,
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = 48,
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addrBag = {
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val sbp = site(SystemBusKey)
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val l2p = site(InclusiveCacheKey)
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val nSets = max(l2p.sets, dcp.nSets)
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val nWays = max(l2p.ways, dcp.nWays)
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val blockOffset = sbp.blockOffset
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val nBeats = min(2, sbp.blockBeats)
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val beatBytes = sbp.beatBytes
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List.tabulate(2 * nWays) { i =>
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Seq.tabulate(nBeats) { j =>
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BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
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}
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}.flatten
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},
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maxRequests = nReqs,
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memStart = memOffset,
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numGens = params.size),
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crossingParams = RocketCrossingParams()
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)
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} ++ prev
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}
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})
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