Bump Rocketchip to June 2020 for Tile changes

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -8,7 +8,7 @@ import chisel3.experimental.annotate
 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem}
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp}
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
@@ -21,13 +21,12 @@ import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
 import midas.targetutils.{MemModelAnnotation}
 import firesim.bridges._
 import firesim.configs.MemModelKey
-import tracegen.HasTraceGenTilesModuleImp
+import tracegen.{TraceGenSystemModuleImp}
 import ariane.ArianeTile
 
 import boom.common.{BoomTile}
 
 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
-import chipyard.{HasChipyardTilesModuleImp}
 import testchipip.{CanHaveTraceIOModuleImp}
 
 object MainMemoryConsts {
@@ -88,12 +87,12 @@ class WithDromajoBridge extends ComposeIOBinder({
 
 
 class WithTraceGenBridge extends OverrideIOBinder({
-  (system: HasTraceGenTilesModuleImp) =>
+  (system: TraceGenSystemModuleImp) =>
     GroundTestBridge(system.clock, system.success)(system.p); Nil
 })
 
 class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
-  (system: HasChipyardTilesModuleImp) => {
+  (system: HasTilesModuleImp) => {
     system.outer.tiles.map {
       case r: RocketTile => {
         annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
@@ -110,7 +109,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
           case _ => Nil
         }
       }
-      case a: ArianeTile => Nil
+      case _ =>
     }
     Nil
   }

generators/firechip/src/main/scala/FireSimMulticlockPOC.scala

@@ -9,11 +9,11 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossi
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.util.{ResetCatchAndSync}
 
-import boom.common.{BoomTilesKey, BoomCrossingKey}
-
 import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
 import firesim.configs._
 
+import boom.common.{WithRationalBoomTiles}
+
 import chipyard.{BuildSystem, DigitalTop, DigitalTopModule}
 import chipyard.config.ConfigValName._
 import chipyard.iobinders.{IOBinders}
@@ -51,15 +51,13 @@ trait HasFireSimClockingImp extends HasAdditionalClocks {
 }
 
 // Config Fragment
-class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => {
-  case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
-  case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
-    r.copy(crossingType = RationalCrossing())
-  }
-  case BoomCrossingKey => up(BoomCrossingKey, site) map { r =>
-    r.copy(crossingType = RationalCrossing())
-  }
-})
+class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config(
+  new WithRationalRocketTiles ++
+  new WithRationalBoomTiles ++
+  new Config((site, here, up) => {
+    case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
+  })
+)
 
 class HalfRateUncore extends WithSingleRationalTileDomain(2,1)
 

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -13,13 +13,11 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.LazyModule
-import boom.common.BoomTilesKey
 import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
-import tracegen.TraceGenKey
+
 import icenet._
-import ariane.ArianeTilesKey
 import testchipip.WithRingSystemBus
 
 import firesim.bridges._
@@ -44,12 +42,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
   case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
 })
 
-class WithPerfCounters extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nPerfCounters = 29)
-  ))
-})
-
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
   case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))