From d1e3cc558bb21be8beb4a883a7ffcad00de9e157 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Fri, 4 Oct 2019 01:09:53 +0000 Subject: [PATCH] firechip: Add FireSimRocketChipSha3L2Config --- build.sbt | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 05a80bba..4d747829 100644 --- a/build.sbt +++ b/build.sbt @@ -188,7 +188,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0e31bb56..d88ffa25 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -138,6 +138,13 @@ class FireSimRocketChipOctaCoreConfig extends Config( new WithNDuplicatedRocketCores(8) ++ new FireSimRocketChipSingleCoreConfig) +// SHA-3 accelerator config +class FireSimRocketChipSha3L2Config extends Config( + new WithInclusiveCache ++ + new sha3.WithSha3Accel ++ + new WithNBigCores(1) ++ + new FireSimRocketChipConfig) + class FireSimBoomConfig extends Config( new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++