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Merge remote-tracking branch 'origin/dev' into firesim-multiclock

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This commit is contained in:
David Biancolin
2020-02-13 12:14:04 -08:00
parent 43008adc8e 7bcedfa7ad
commit d19ca81e61
116 changed files with 2550 additions and 3817 deletions
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11
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -10,7 +10,7 @@ import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
import icenet.HasPeripheryIceNICModuleImpValidOnly
import junctions.{NastiKey, NastiParameters}
@@ -21,18 +21,18 @@ import firesim.util.RegisterBridgeBinder
import tracegen.HasTraceGenTilesModuleImp
class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
target.debug.clockeddmi.foreach({ cdmi =>
target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
cdmi.dmi.req.valid := false.B
cdmi.dmi.req.bits := DontCare
cdmi.dmi.resp.ready := false.B
cdmi.dmiClock := false.B.asClock
cdmi.dmiReset := false.B
})
}))
Seq()
})
class WithSerialBridge extends RegisterBridgeBinder({
case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial)(target.p))
case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial.get)(target.p))
})
class WithNICBridge extends RegisterBridgeBinder({
@@ -44,7 +44,8 @@ class WithUARTBridge extends RegisterBridgeBinder({
})
class WithBlockDeviceBridge extends RegisterBridgeBinder({
case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.clock ,target.bdev, target.reset.toBool)(target.p))
case target: CanHavePeripheryBlockDeviceModuleImp =>
Seq(BlockDevBridge(target.clock, target.bdev.get, target.reset.toBool)(target.p))
})
class WithFASEDBridge extends RegisterBridgeBinder({