Merge remote-tracking branch 'origin/dev' into firesim-multiclock

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -10,7 +10,7 @@ import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
 import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 
-import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
+import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
 import icenet.HasPeripheryIceNICModuleImpValidOnly
 
 import junctions.{NastiKey, NastiParameters}
@@ -21,18 +21,18 @@ import firesim.util.RegisterBridgeBinder
 import tracegen.HasTraceGenTilesModuleImp
 
 class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
-  target.debug.clockeddmi.foreach({ cdmi =>
+  target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
     cdmi.dmi.req.valid := false.B
     cdmi.dmi.req.bits := DontCare
     cdmi.dmi.resp.ready := false.B
     cdmi.dmiClock := false.B.asClock
     cdmi.dmiReset := false.B
-  })
+  }))
   Seq()
 })
 
 class WithSerialBridge extends RegisterBridgeBinder({
-  case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial)(target.p))
+  case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial.get)(target.p))
 })
 
 class WithNICBridge extends RegisterBridgeBinder({
@@ -44,7 +44,8 @@ class WithUARTBridge extends RegisterBridgeBinder({
 })
 
 class WithBlockDeviceBridge extends RegisterBridgeBinder({
-  case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.clock ,target.bdev, target.reset.toBool)(target.p))
+  case target: CanHavePeripheryBlockDeviceModuleImp =>
+    Seq(BlockDevBridge(target.clock, target.bdev.get, target.reset.toBool)(target.p))
 })
 
 class WithFASEDBridge extends RegisterBridgeBinder({

generators/firechip/src/main/scala/Generator.scala

@@ -4,7 +4,7 @@ package firesim.firesim
 
 import java.io.{File, FileWriter}
 
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.internal.firrtl.{Circuit, Port}
 
 import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
@@ -18,6 +18,8 @@ import freechips.rocketchip.tile.XLen
 
 import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
 
+import scala.util.Try
+
 import utilities.TestSuiteHelper
 
 trait HasTestSuites {
@@ -28,6 +30,14 @@ trait HasTestSuites {
     TestGeneration.addSuite(SlowBlockdevTests)
     if (!targetName.contains("NoNIC"))
       TestGeneration.addSuite(NICLoopbackTests)
+
+    import hwacha.HwachaTestSuites._
+    if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
+      TestGeneration.addSuites(rv64uv.map(_("p")))
+      TestGeneration.addSuites(rv64uv.map(_("vp")))
+      TestGeneration.addSuite(rv64sv("p"))
+      TestGeneration.addSuite(hwachaBmarks)
+    }
   }
 }
 
@@ -48,7 +58,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
 }
 
 object FireSimGenerator extends App with IsFireSimGeneratorLike {
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
   // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
@@ -60,7 +70,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
 
 // For now, provide a separate generator app when not specifically building for FireSim
 object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
   generateTestSuiteMakefrags

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -10,10 +10,10 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
-import freechips.rocketchip.devices.debug.DebugModuleParams
+import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.{RationalCrossing}
-import boom.common.{BoomCrossingKey, BoomTilesKey}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig}
+import boom.common.{BoomTilesKey, BoomCrossingKey}
+import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 import tracegen.TraceGenKey
@@ -48,12 +48,17 @@ class WithUARTKey extends Config((site, here, up) => {
      nRxEntries = 256))
 })
 
+class WithSerial extends Config((site, here, up) => {
+  case SerialKey => true
+})
+
 class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
 
 class WithNICKey extends Config((site, here, up) => {
-  case NICKey => NICConfig(
+  case NICKey => Some(NICConfig(
     inBufFlits = 8192,
-    ctrlQueueDepth = 64)
+    ctrlQueueDepth = 64,
+    checksumOffload = true))
 })
 
 class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -82,7 +87,7 @@ class WithBoomEnableTrace extends Config((site, here, up) => {
 
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
-  case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false)
+  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
 })
 
 // Testing configurations
@@ -116,6 +121,7 @@ class FireSimRocketChipConfig extends Config(
   new WithoutTLMonitors ++
   new WithUARTKey ++
   new WithNICKey ++
+  new WithSerial ++
   new WithBlockDevice ++
   new WithRocketL2TLBs(1024) ++
   new WithPerfCounters ++
@@ -173,6 +179,7 @@ class FireSimBoomConfig extends Config(
   new WithoutTLMonitors ++
   new WithUARTKey ++
   new WithNICKey ++
+  new WithSerial ++
   new WithBlockDevice ++
   new WithBoomEnableTrace ++
   new WithBoomL2TLBs(1024) ++
@@ -214,6 +221,18 @@ class FireSimRocketBoomConfig extends Config(
   new FireSimBoomConfig
 )
 
+//**********************************************************************************
+//* Gemmini Configurations
+//*********************************************************************************/
+
+// Gemmini systolic accelerator default config
+class FireSimRocketChipGemminiL2Config extends Config(
+  new WithInclusiveCache ++
+  new gemmini.DefaultGemminiConfig ++
+  new WithNBigCores(1) ++
+  new FireSimRocketChipConfig)
+
+
 //**********************************************************************************
 //* Supernode Configurations
 //*********************************************************************************/

generators/firechip/src/main/scala/Targets.scala

@@ -42,10 +42,10 @@ class FireSimDUT(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasPeripherySerial
+    with CanHavePeripherySerial
     with HasPeripheryUART
-    with HasPeripheryIceNIC
-    with HasPeripheryBlockDevice
+    with CanHavePeripheryIceNIC
+    with CanHavePeripheryBlockDevice
     with HasTraceIO
 {
   override lazy val module = new FireSimModuleImp(this)
@@ -55,10 +55,10 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasPeripherySerialModuleImp
+    with CanHavePeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripheryIceNICModuleImpValidOnly
-    with HasPeripheryBlockDeviceModuleImp
+    with CanHavePeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with HasFireSimClockingImp
     with CanHaveMultiCycleRegfileImp
@@ -69,9 +69,9 @@ class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasPeripherySerial
+    with CanHavePeripherySerial
     with HasPeripheryUART
-    with HasPeripheryBlockDevice
+    with CanHavePeripheryBlockDevice
     with HasTraceIO
 {
   override lazy val module = new FireSimNoNICModuleImp(this)
@@ -81,9 +81,9 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasPeripherySerialModuleImp
+    with CanHavePeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
-    with HasPeripheryBlockDeviceModuleImp
+    with CanHavePeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with HasFireSimClockingImp
     with CanHaveMultiCycleRegfileImp
@@ -109,12 +109,11 @@ class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(()
 
 // Verilog blackbox integration demo
 class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT
-    with example.HasPeripheryGCD
+    with example.CanHavePeripheryGCD
 {
   override lazy val module = new FireSimVerilogGCDModuleImp(this)
 }
 
 class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l)
-    with example.HasPeripheryGCDModuleImp
 
 class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT)