slightly more clarity in the diplomacy example [skip ci]
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@@ -98,18 +98,19 @@ This example shows a Rocket Chip based SoC that merges multiple system component
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with HasPeripheryUARTModuleImp
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with HasPeripheryUARTModuleImp
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with HasPeripheryIceNICModuleImp
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with HasPeripheryIceNICModuleImp
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There are two "cakes" here. One for the lazy module and one for the module
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There are two "cakes" here. One for the lazy module (ex. ``HasNoDebug``) and one for the lazy module
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implementation. The lazy module defines all the logical connections between
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implementation (ex. ``HasNoDebugModuleImp`` where ``Imp`` refers to implementation). The lazy module defines
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generators and exchanges configuration information among them, while the
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all the logical connections between generators and exchanges configuration information among them, while the
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module implementation performs the actual Chisel RTL elaboration.
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lazy module implementation performs the actual Chisel RTL elaboration.
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In the MySoC example class, the "outer" ``MySoC`` instantiates the "inner"
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In the MySoC example class, the "outer" ``MySoC`` instantiates the "inner"
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``MySoCModuleImp`` as a lazy module. This delays immediate elaboration
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``MySoCModuleImp`` as a lazy module implementation. This delays immediate elaboration
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of the module. The ``RocketSubsystem`` outer base class, as well as the
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of the module until all logical connections are determined and all configuration information is exchanged.
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The ``RocketSubsystem`` outer base class, as well as the
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``HasPeripheryX`` outer traits contain code to perform high-level logical
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``HasPeripheryX`` outer traits contain code to perform high-level logical
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connections. For example, the ``HasPeripherySerial`` outer trait contains code
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connections. For example, the ``HasPeripherySerial`` outer trait contains code
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to lazily instantiate the ``SerialAdapter``, and connect the SerialAdapter's
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to lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s
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TileLink node to the frontbus.
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TileLink node to the Front bus.
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The ``ModuleImp`` classes and traits perform elaboration of real RTL.
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The ``ModuleImp`` classes and traits perform elaboration of real RTL.
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For example, the ``HasPeripherySerialModuleImp`` trait physically connects
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For example, the ``HasPeripherySerialModuleImp`` trait physically connects
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@@ -121,12 +122,12 @@ After elaboration, the result will be a MySoC module, which contains a
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SerialAdapter module (among others).
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SerialAdapter module (among others).
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From a high level, classes which extend LazyModule *must* reference
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From a high level, classes which extend LazyModule *must* reference
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their module implementation through``lazy val module``, and they
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their module implementation through ``lazy val module``, and they
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*may* optionally reference other lazy modules (which will elaborate
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*may* optionally reference other lazy modules (which will elaborate
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as child modules in the module hierarchy). The "inner" modules
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as child modules in the module hierarchy). The "inner" modules
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contain the implementation for the module, and may instantiate
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contain the implementation for the module, and may instantiate
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other normal modules OR lazy modules (for nested Diplomacy
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other normal modules OR lazy modules (for nested Diplomacy
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graphs, for example. This is very advanced).
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graphs, for example).
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Mix-in
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Mix-in
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---------------------------
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---------------------------
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