[firechip] remove fireboom DUT, remove ExcludeInvalidBoomAssertions mixin

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -187,6 +187,19 @@ class FireSimBoomQuadCoreConfig extends Config(
   new WithNDuplicatedBoomCores(4) ++
   new FireSimBoomConfig)
 
+//**********************************************************************************
+//* Heterogeneous Configurations
+//*********************************************************************************/
+
+// dual core config (rocket + small boom)
+class FireSimRocketBoomConfig extends Config(
+  new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
+  new boom.common.WithRenumberHarts ++ // fix hart numbering
+  new boom.common.WithSmallBooms ++ // change single BOOM to small
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
+  new FireSimBoomConfig
+)
+
 //**********************************************************************************
 //* Supernode Configurations
 //*********************************************************************************/

generators/firechip/src/main/scala/TargetMixins.scala

@@ -14,7 +14,9 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.TracedInstruction
 import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
 
-import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
+import midas.targetutils.MemModelAnnotation
+
+import boom.common.BoomTile
 
 import boom.common.BoomTile
 
@@ -50,11 +52,6 @@ trait HasTraceIOImp extends LazyModuleImp {
   }
 }
 
-// Prevent MIDAS from synthesizing assertions in the dummy TLB included in BOOM
-trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
-  ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
-}
-
 trait CanHaveMultiCycleRegfileImp {
   val outer: utilities.HasBoomAndRocketTiles
 

generators/firechip/src/main/scala/Targets.scala

@@ -86,61 +86,8 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule
     with HasTraceIOImp
     with CanHaveMultiCycleRegfileImp
 
-
 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
 
-class FireBoomDUT(implicit p: Parameters) extends Subsystem
-    with HasHierarchicalBusTopology
-    with CanHaveMasterAXI4MemPort
-    with HasPeripheryBootROM
-    with HasPeripherySerial
-    with HasPeripheryUART
-    with HasPeripheryIceNIC
-    with HasPeripheryBlockDevice
-    with HasTraceIO
-{
-  override lazy val module = new FireBoomModuleImp(this)
-}
-
-class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l)
-    with HasRTCModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-    with HasPeripheryBootROMModuleImp
-    with HasPeripherySerialModuleImp
-    with HasPeripheryUARTModuleImp
-    with HasPeripheryIceNICModuleImpValidOnly
-    with HasPeripheryBlockDeviceModuleImp
-    with HasTraceIOImp
-    with ExcludeInvalidBoomAssertions
-    with CanHaveMultiCycleRegfileImp
-
-class FireBoom(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomDUT)
-
-class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
-    with HasHierarchicalBusTopology
-    with CanHaveMasterAXI4MemPort
-    with HasPeripheryBootROM
-    with HasPeripherySerial
-    with HasPeripheryUART
-    with HasPeripheryBlockDevice
-    with HasTraceIO
-{
-  override lazy val module = new FireBoomNoNICModuleImp(this)
-}
-
-class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModuleImp(l)
-    with HasRTCModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-    with HasPeripheryBootROMModuleImp
-    with HasPeripherySerialModuleImp
-    with HasPeripheryUARTModuleImp
-    with HasPeripheryBlockDeviceModuleImp
-    with HasTraceIOImp
-    with ExcludeInvalidBoomAssertions
-    with CanHaveMultiCycleRegfileImp
-
-class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomNoNICDUT)
-
 class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
     with HasHierarchicalBusTopology
     with HasTraceGenTiles