From cdcaf5c57471f59f5e430e65209038fb2aafe7ee Mon Sep 17 00:00:00 2001
From: Paul Rigge <rigge@berkeley.edu>
Date: Tue, 26 May 2020 22:29:50 -0700
Subject: [PATCH] Missed an include end

---
 generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 05559662..b1001c59 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -464,7 +464,7 @@ class StreamingFIRRocketConfig extends Config (
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new freechips.rocketchip.system.BaseConfig)
-// DOC include end: FIRRocketConfig
+// DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++