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Refactor memory compiler, again

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This commit is contained in:
Edward Wang
2017-07-28 12:49:29 -07:00
committed by edwardcwang
parent 937b053b15
commit cca6c0ea7e
1 changed files with 18 additions and 5 deletions
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23
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -52,8 +52,10 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
mdf.macrolib.Utils.writeMDFToPath(Some(concat(memPrefix, mem)), mems) mdf.macrolib.Utils.writeMDFToPath(Some(concat(memPrefix, mem)), mems)
} }
// Execute the macro compiler and compare FIRRTL outputs. // Execute the macro compiler and compare FIRRTL outputs after reparsing output.
// TODO: think of a less brittle way to test this? def execute(memFile: String, libFile: Option[String], synflops: Boolean, output: String): Unit = {
execute(Some(memFile), libFile, synflops, output)
}
def execute(memFile: String, libFile: String, synflops: Boolean, output: String): Unit = { def execute(memFile: String, libFile: String, synflops: Boolean, output: String): Unit = {
execute(Some(memFile), Some(libFile), synflops, output) execute(Some(memFile), Some(libFile), synflops, output)
} }
@@ -245,14 +247,13 @@ circuit $mem_name :
""" """
} }
// Generate the footer (contains the target memory extmodule). // Generate the target memory ports.
def generateFooter(): String = { def generateFooterPorts(): String = {
require (libSRAM.ports.size == 1, "Footer generator only supports single port lib") require (libSRAM.ports.size == 1, "Footer generator only supports single port lib")
val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input lib_read_en : UInt<1>" else "" val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input lib_read_en : UInt<1>" else ""
val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else "" val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else ""
s""" s"""
extmodule $lib_name :
input lib_clk : Clock input lib_clk : Clock
input lib_addr : UInt<$lib_addr_width> input lib_addr : UInt<$lib_addr_width>
input lib_din : UInt<$libWidth> input lib_din : UInt<$libWidth>
@@ -260,6 +261,18 @@ circuit $mem_name :
${readEnable} ${readEnable}
input lib_write_en : UInt<1> input lib_write_en : UInt<1>
${footerMask} ${footerMask}
"""
}
// Generate the footer (contains the target memory extmodule declaration by default).
def generateFooter(): String = {
require (libSRAM.ports.size == 1, "Footer generator only supports single port lib")
val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input lib_read_en : UInt<1>" else ""
val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else ""
s"""
extmodule $lib_name :
${generateFooterPorts}
defname = $lib_name defname = $lib_name
""" """