wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[clocking] Address some of Colin's PR comments

Browse Source
This commit is contained in:
David Biancolin
2020-09-24 23:28:47 -07:00
parent f6989a1968
commit cc949aadab
2 changed files with 1 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
generators/chipyard/src/main/scala/ConfigFragments.scala
View File

@@ -28,9 +28,6 @@ import sifive.blocks.devices.spi._
import chipyard._ import chipyard._
// Imports for multiclock sketch
import boom.common.{BoomTile, BoomTileParams}
import ariane.{ArianeTile, ArianeTileParams}
// ----------------------- // -----------------------
// Common Config Fragments // Common Config Fragments
// ----------------------- // -----------------------
@@ -167,7 +164,6 @@ class WithDMIDTM extends Config((site, here, up) => {
class WithNoDebug extends Config((site, here, up) => { class WithNoDebug extends Config((site, here, up) => {
case DebugModuleKey => None case DebugModuleKey => None
}) })
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)

2
generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
View File

@@ -55,7 +55,7 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
) )
/** /**
* Generates a digttal-divider-only PLL model that verilator can simulate. * Generates a digital-divider-only PLL model that verilator can simulate.
* Inspects all take-specified frequencies in the output ClockGroup, calculates a * Inspects all take-specified frequencies in the output ClockGroup, calculates a
* fast reference clock (roughly LCM(requested frequencies)) which is passed up the * fast reference clock (roughly LCM(requested frequencies)) which is passed up the
* diplomatic graph, and then generates dividers for each unique requested * diplomatic graph, and then generates dividers for each unique requested