From cbf5f9fb6273c74e928de3fa7b2c39d99d9c6c2e Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Tue, 15 Feb 2022 18:17:47 -0800 Subject: [PATCH] adding FSDB note --- docs/VLSI/ASAP7-Tutorial.rst | 2 +- docs/VLSI/Sky130-Tutorial.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index d881376a..b147d6a5 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -152,7 +152,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively. -Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. +Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. Power/Rail Analysis ^^^^^^^^^^^^^^^^^^^ diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Tutorial.rst index f004dec4..2a9c19b1 100644 --- a/docs/VLSI/Sky130-Tutorial.rst +++ b/docs/VLSI/Sky130-Tutorial.rst @@ -142,7 +142,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively. -Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. +Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets. Power/Rail Analysis ^^^^^^^^^^^^^^^^^^^