From cb79078641551d46c733d86436b5c0fb6b243fdf Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 3 Aug 2017 23:28:43 +0000 Subject: [PATCH] get rid of tlserdes project --- src/main/scala/tlserdes/Configs.scala | 14 ---- src/main/scala/tlserdes/Periphery.scala | 95 ----------------------- src/main/scala/tlserdes/TestHarness.scala | 20 ----- src/main/scala/tlserdes/Top.scala | 27 ------- 4 files changed, 156 deletions(-) delete mode 100644 src/main/scala/tlserdes/Configs.scala delete mode 100644 src/main/scala/tlserdes/Periphery.scala delete mode 100644 src/main/scala/tlserdes/TestHarness.scala delete mode 100644 src/main/scala/tlserdes/Top.scala diff --git a/src/main/scala/tlserdes/Configs.scala b/src/main/scala/tlserdes/Configs.scala deleted file mode 100644 index 56a76c65..00000000 --- a/src/main/scala/tlserdes/Configs.scala +++ /dev/null @@ -1,14 +0,0 @@ -package tlserdes - -import freechips.rocketchip.config.{Parameters, Config} - -class WithTLSerdes extends Config((site, here, up) => { - case TLSerdesWidth => 16 -}) - -class DefaultSerdesConfig extends Config( - new WithTLSerdes ++ - new freechips.rocketchip.chip.DefaultConfig) - -class WithTwoMemChannels extends example.WithTwoMemChannels -class WithFourMemChannels extends example.WithFourMemChannels diff --git a/src/main/scala/tlserdes/Periphery.scala b/src/main/scala/tlserdes/Periphery.scala deleted file mode 100644 index f37168ee..00000000 --- a/src/main/scala/tlserdes/Periphery.scala +++ /dev/null @@ -1,95 +0,0 @@ -package tlserdes - -import chisel3._ -import chisel3.util._ -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.chip.{ExtMem, HasSystemNetworks} -import freechips.rocketchip.coreplex.{BankedL2Config, CacheBlockBytes} -import freechips.rocketchip.tilelink._ -import testchipip._ - -case object TLSerdesWidth extends Field[Int] - -class TLSerdesMem(implicit p: Parameters) extends LazyModule { - val config = p(ExtMem) - val channels = p(BankedL2Config).nMemoryChannels - val serdesWidth = p(TLSerdesWidth) - val blockBytes = p(CacheBlockBytes) - - val desser = LazyModule(new TLDesser(serdesWidth, - Seq.tabulate(channels) { ch => - TLClientParameters( - name = s"tl-desser$ch", sourceId = IdRange(0, 1 << config.idBits)) - })) - - for (ch <- 0 until channels) { - val base = AddressSet(config.base, config.size-1) - val filter = AddressSet(ch * blockBytes, ~((channels-1) * blockBytes)) - - val mem = LazyModule(new TLRAM( - address = base.intersect(filter).get, - executable = true, - beatBytes = config.beatBytes)) - - mem.node := TLBuffer()( - TLFragmenter(config.beatBytes, blockBytes)(desser.node)) - } - - lazy val module = new LazyModuleImp(this) { - val io = IO(new Bundle { - val ser = Vec(channels, new SerialIO(serdesWidth)) - }) - - desser.module.io.ser <> io.ser - } -} - -trait HasPeripheryTLSerdesMemPort extends HasSystemNetworks { - private val config = p(ExtMem) - private val channels = p(BankedL2Config).nMemoryChannels - private val serdesWidth = p(TLSerdesWidth) - private val blockBytes = p(CacheBlockBytes) - private val device = new MemoryDevice - - val serdes = LazyModule(new TLSerdes( - w = serdesWidth, - params = Seq.tabulate(channels) { ch => - val base = AddressSet(config.base, config.size-1) - val filter = AddressSet(ch * blockBytes, ~((channels-1) * blockBytes)) - - TLManagerParameters( - address = base.intersect(filter).toSeq, - resources = device.reg, - regionType = RegionType.UNCACHED, - executable = true, - supportsGet = TransferSizes(1, blockBytes), - supportsPutFull = TransferSizes(1, blockBytes), - supportsPutPartial = TransferSizes(1, blockBytes), - fifoId = Some(0)) - }, - beatBytes = config.beatBytes)) - - mem.foreach { xbar => - serdes.node := - TLBuffer()( - TLAtomicAutomata()( - TLSourceShrinker(1 << config.idBits)(xbar.node))) - } -} - -trait HasPeripheryTLSerdesMemPortModuleImp extends LazyMultiIOModuleImp { - private val serdesWidth = p(TLSerdesWidth) - private val config = p(ExtMem) - private val channels = p(BankedL2Config).nMemoryChannels - - val outer: HasPeripheryTLSerdesMemPort - val tlser = IO(Vec(channels, new SerialIO(serdesWidth))) - - tlser <> outer.serdes.module.io.ser - - def connectSerdesMem(dummy: Int = 0) { - val memser = Module(LazyModule(new TLSerdesMem).module).io.ser - memser.zip(tlser).foreach { case (mem, tl) => mem.connect(tl) } - } -} diff --git a/src/main/scala/tlserdes/TestHarness.scala b/src/main/scala/tlserdes/TestHarness.scala deleted file mode 100644 index 4aaca709..00000000 --- a/src/main/scala/tlserdes/TestHarness.scala +++ /dev/null @@ -1,20 +0,0 @@ -package tlserdes - -import chisel3._ -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.config.{Field, Parameters} -import testchipip.GeneratorApp - -class TestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - val dut = Module(LazyModule(new SerdesTop).module) - dut.connectSerdesMem() - io.success := dut.connectSimSerial() -} - -object Generator extends GeneratorApp { - generateFirrtl -} diff --git a/src/main/scala/tlserdes/Top.scala b/src/main/scala/tlserdes/Top.scala deleted file mode 100644 index 113f4348..00000000 --- a/src/main/scala/tlserdes/Top.scala +++ /dev/null @@ -1,27 +0,0 @@ -package tlserdes - -import chisel3._ -import chisel3.util._ -import freechips.rocketchip.chip._ -import freechips.rocketchip.config.Parameters -import testchipip._ - -class SerdesTop(implicit p: Parameters) extends BaseSystem - with HasPeripheryTLSerdesMemPort - with HasPeripheryErrorSlave - with HasPeripheryZeroSlave - with HasPeripheryBootROM - with HasPeripheryRTCCounter - with HasRocketPlexMaster - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new SerdesTopModule(this) -} - -class SerdesTopModule(outer: SerdesTop) extends BaseSystemModule(outer) - with HasPeripheryTLSerdesMemPortModuleImp - with HasPeripheryBootROMModuleImp - with HasPeripheryRTCCounterModuleImp - with HasRocketPlexMasterModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp