diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index 550be3c2..f4603bfc 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -67,11 +67,11 @@ model_dir_debug = $(build_dir)/$(long_name).debug
 #########################################################################################
 # vcs simulator rules
 #########################################################################################
-$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
+$(sim): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir)
 	$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir)
 
-$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
+$(sim_debug): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug)  \
 	+define+DEBUG -debug_access+all -kdb -lca
diff --git a/vcs.mk b/vcs.mk
index 6b5eb80b..2f8c3d0e 100644
--- a/vcs.mk
+++ b/vcs.mk
@@ -51,8 +51,7 @@ VCS_NONCC_OPTS = \
 	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
-	+incdir+$(build_dir) \
-	$(sim_vsrcs)
+	+incdir+$(build_dir)
 
 PREPROC_DEFINES = \
 	+define+VCS \