Move IOCell files
This commit is contained in:
Jerry Zhao
11
generators/chipyard/src/main/resources/vsrc/Analog.v
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11
generators/chipyard/src/main/resources/vsrc/Analog.v
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// See LICENSE for license details
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`timescale 1ns/1ps
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module AnalogConst #(CONST, WIDTH) (
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output [WIDTH-1:0] io
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);
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assign io = CONST;
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endmodule
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18
generators/chipyard/src/main/scala/iocell/Analog.scala
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18
generators/chipyard/src/main/scala/iocell/Analog.scala
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// See LICENSE for license details
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package barstools.iocell.chisel
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import chisel3._
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import chisel3.util.{HasBlackBoxResource}
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import chisel3.experimental.{Analog, IntParam}
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class AnalogConst(value: Int, width: Int = 1)
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extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width)))
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with HasBlackBoxResource {
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val io = IO(new Bundle { val io = Analog(width.W) })
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addResource("/barstools/iocell/vsrc/Analog.v")
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}
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object AnalogConst {
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def apply(value: Int, width: Int = 1) = Module(new AnalogConst(value, width)).io.io
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}
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338
generators/chipyard/src/main/scala/iocell/IOCell.scala
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338
generators/chipyard/src/main/scala/iocell/IOCell.scala
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// See LICENSE for license details
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package barstools.iocell.chisel
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import chisel3._
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import chisel3.util.{Cat, HasBlackBoxInline}
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import chisel3.reflect.DataMirror
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import chisel3.experimental.{Analog, BaseModule}
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// The following four IO cell bundle types are bare-minimum functional connections
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// for modeling 4 different IO cell scenarios. The intention is that the user
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// would create wrapper modules that extend these interfaces with additional
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// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles
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// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
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// but we want to avoid a dependency on an external libraries.
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/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
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* pad: off-chip (external) connection
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* core: internal connection
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*/
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class AnalogIOCellBundle extends Bundle {
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val pad = Analog(1.W) // Pad/bump signal (off-chip)
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val core = Analog(1.W) // core signal (on-chip)
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}
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/** The base IO bundle for a signal with runtime-controllable direction
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* pad: off-chip (external) connection
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* i: input to chip logic (output from IO cell)
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* ie: enable signal for i
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* o: output from chip logic (input to IO cell)
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* oe: enable signal for o
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*/
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class DigitalGPIOCellBundle extends Bundle {
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val pad = Analog(1.W)
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val i = Output(Bool())
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val ie = Input(Bool())
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val o = Input(Bool())
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val oe = Input(Bool())
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}
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/** The base IO bundle for a digital output signal
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* pad: off-chip (external) connection
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* o: output from chip logic (input to IO cell)
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* oe: enable signal for o
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*/
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class DigitalOutIOCellBundle extends Bundle {
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val pad = Output(Bool())
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val o = Input(Bool())
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val oe = Input(Bool())
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}
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/** The base IO bundle for a digital input signal
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* pad: off-chip (external) connection
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* i: input to chip logic (output from IO cell)
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* ie: enable signal for i
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*/
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class DigitalInIOCellBundle extends Bundle {
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val pad = Input(Bool())
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val i = Output(Bool())
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val ie = Input(Bool())
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}
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trait IOCell extends BaseModule {
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var iocell_name: Option[String] = None
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/** Set IOCell name
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* @param s Proposed name for the IOCell
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*
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* @return An inherited IOCell with given the proposed name
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*/
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def suggestName(s: String): this.type = {
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iocell_name = Some(s)
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super.suggestName(s)
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}
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}
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trait AnalogIOCell extends IOCell {
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val io: AnalogIOCellBundle
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}
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trait DigitalGPIOCell extends IOCell {
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val io: DigitalGPIOCellBundle
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}
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trait DigitalInIOCell extends IOCell {
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val io: DigitalInIOCellBundle
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}
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trait DigitalOutIOCell extends IOCell {
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val io: DigitalOutIOCellBundle
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}
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// The following Generic IO cell black boxes have verilog models that mimic a very simple
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// implementation of an IO cell. For building a real chip, it is important to implement
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// and use similar classes which wrap the foundry-specific IO cells.
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abstract class GenericIOCell extends BlackBox with HasBlackBoxInline {
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val impl: String
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val moduleName = this.getClass.getSimpleName
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setInline(s"$moduleName.v", impl);
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}
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class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell {
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val io = IO(new AnalogIOCellBundle)
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lazy val impl = s"""
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`timescale 1ns/1ps
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module GenericAnalogIOCell(
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inout pad,
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inout core
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);
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assign core = 1'bz;
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assign pad = core;
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endmodule"""
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}
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class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell {
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val io = IO(new DigitalGPIOCellBundle)
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lazy val impl = s"""
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`timescale 1ns/1ps
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module GenericDigitalGPIOCell(
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inout pad,
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output i,
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input ie,
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input o,
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input oe
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);
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assign pad = oe ? o : 1'bz;
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assign i = ie ? pad : 1'b0;
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endmodule"""
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}
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class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell {
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val io = IO(new DigitalInIOCellBundle)
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lazy val impl = s"""
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`timescale 1ns/1ps
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module GenericDigitalInIOCell(
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input pad,
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output i,
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input ie
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);
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assign i = ie ? pad : 1'b0;
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endmodule"""
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}
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class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
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val io = IO(new DigitalOutIOCellBundle)
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lazy val impl = s"""
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`timescale 1ns/1ps
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module GenericDigitalOutIOCell(
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output pad,
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input o,
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input oe
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);
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assign pad = oe ? o : 1'bz;
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endmodule"""
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}
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trait IOCellTypeParams {
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def analog(): AnalogIOCell
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def gpio(): DigitalGPIOCell
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def input(): DigitalInIOCell
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def output(): DigitalOutIOCell
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}
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case class GenericIOCellParams() extends IOCellTypeParams {
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def analog() = Module(new GenericAnalogIOCell)
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def gpio() = Module(new GenericDigitalGPIOCell)
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def input() = Module(new GenericDigitalInIOCell)
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def output() = Module(new GenericDigitalOutIOCell)
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}
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object IOCell {
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/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
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* signal and return the new IO and a Seq containing all generated IO cells.
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* @param coreSignal The signal onto which to add IO cells
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* @param name An optional name or name prefix to use for naming IO cells
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* @param abstractResetAsAsync When set, will coerce abstract resets to
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* AsyncReset, and otherwise to Bool (sync reset)
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* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
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*/
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def generateIOFromSignal[T <: Data](
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coreSignal: T,
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name: String,
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typeParams: IOCellTypeParams = GenericIOCellParams(),
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abstractResetAsAsync: Boolean = false
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): (T, Seq[IOCell]) = {
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val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
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val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
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val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
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(padSignal, iocells)
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}
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/** Connect two identical signals together by adding IO cells between them and return a Seq
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* containing all generated IO cells.
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* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
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* @param padSignal The pad-side (external) signal onto which to connect IO cells
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* @param name An optional name or name prefix to use for naming IO cells
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* @return A Seq of all generated IO cell instances
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*/
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val toSyncReset: (Reset) => Bool = _.asBool
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val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
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def generateFromSignal[T <: Data, R <: Reset](
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coreSignal: T,
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padSignal: T,
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name: Option[String] = None,
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typeParams: IOCellTypeParams = GenericIOCellParams(),
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concretizeResetFn: (Reset) => R = toSyncReset
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): Seq[IOCell] = {
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def genCell[T <: Data](
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castToBool: (T) => Bool,
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castFromBool: (Bool) => T
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)(coreSignal: T,
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padSignal: T
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): Seq[IOCell] = {
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DataMirror.directionOf(coreSignal) match {
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case ActualDirection.Input => {
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val iocell = typeParams.input()
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name.foreach(n => {
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iocell.suggestName(n)
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})
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coreSignal := castFromBool(iocell.io.i)
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iocell.io.ie := true.B
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iocell.io.pad := castToBool(padSignal)
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Seq(iocell)
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}
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case ActualDirection.Output => {
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val iocell = typeParams.output()
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name.foreach(n => {
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iocell.suggestName(n)
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})
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iocell.io.o := castToBool(coreSignal)
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iocell.io.oe := true.B
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padSignal := castFromBool(iocell.io.pad)
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Seq(iocell)
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}
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case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell")
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}
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}
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def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _
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def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _
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def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _
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(coreSignal, padSignal) match {
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case (coreSignal: Analog, padSignal: Analog) => {
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if (coreSignal.getWidth == 0) {
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Seq()
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} else {
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require(
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coreSignal.getWidth == 1,
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"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
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)
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val iocell = typeParams.analog()
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name.foreach(n => iocell.suggestName(n))
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iocell.io.core <> coreSignal
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padSignal <> iocell.io.pad
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Seq(iocell)
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}
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}
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case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
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case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
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case (coreSignal: Bits, padSignal: Bits) => {
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require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
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if (padSignal.getWidth == 0) {
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// This dummy assignment will prevent invalid firrtl from being emitted
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DataMirror.directionOf(coreSignal) match {
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case ActualDirection.Input => coreSignal := 0.U
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case _ => {}
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}
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Seq()
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} else {
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DataMirror.directionOf(coreSignal) match {
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case ActualDirection.Input => {
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val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) =>
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val iocell = typeParams.input()
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// Note that we are relying on chisel deterministically naming this in the index order (which it does)
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// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
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// An alternative solution would be to suggestName(n + "_" + i)
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name.foreach(n => {
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iocell.suggestName(n)
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})
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iocell.io.pad := sig
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iocell.io.ie := true.B
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iocell
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}
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// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
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coreSignal := Cat(iocells.map(_.io.i).reverse)
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iocells
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}
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case ActualDirection.Output => {
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val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) =>
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val iocell = typeParams.output()
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// Note that we are relying on chisel deterministically naming this in the index order (which it does)
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// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
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// An alternative solution would be to suggestName(n + "_" + i)
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name.foreach(n => {
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iocell.suggestName(n)
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})
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iocell.io.o := sig
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iocell.io.oe := true.B
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iocell
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}
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// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
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padSignal := Cat(iocells.map(_.io.pad).reverse)
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iocells
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}
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case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)")
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}
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}
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}
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case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
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case (coreSignal: Vec[_], padSignal: Vec[_]) => {
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require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
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coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
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val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams)
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total ++ ios
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}
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}
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case (coreSignal: Record, padSignal: Record) => {
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coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
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val pad = padSignal.elements(eltName)
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val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams)
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total ++ ios
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}
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}
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case _ => { throw new Exception("Oops, I don't know how to handle this signal.") }
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}
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}
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}
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