diff --git a/.circleci/README.md b/.circleci/README.md index 018b4b57..83fd3264 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -1,7 +1,7 @@ Chipyard CI =========== -Website: https://circleci.com/gh/ucb-bar/project-template +Website: https://circleci.com/gh/ucb-bar/chipyard CircleCI Brief Explanation --------------------------- @@ -35,11 +35,12 @@ Here the key is built from a string where the `checksum` portion converts the fi This directory contains all the collateral for the Chipyard CI to work. The following is included: - build-toolchains.sh # build either riscv-tools or esp-tools - build-verilator.sh # build verilator - create-hash.sh # create hashes of riscv-tools/esp-tools so circleci caching can work - do-rtl-build.sh # use verilator to build a sim executable - config.yml # main circleci config script to enumerate jobs/workflows + `build-toolchains.sh` # build either riscv-tools or esp-tools + `build-verilator.sh` # build verilator (remotely) + `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work + `do-rtl-build.sh` # use verilator to build a sim executable (remotely) + `config.yml` # main circleci config script to enumerate jobs/workflows + `defaults.sh` # default variables used How things are setup for Chipyard --------------------------------- @@ -52,3 +53,18 @@ The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` i This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). 4th, finally run the tests that were wanted. + +Other CI Setup +-------------- + +To get the CI to work correctly you need to setup CircleCI environment variables to point to the remote directory to build files and the server user/ip. +In the project settings, you can find this under "Build Settings" "Environment Variables". +You need to add two variables like the following: + +CI\_DIR = /path/to/where/you/want/to/store/remote/files +SERVER = username@myserver.coolmachine.berkeley.edu + +Additionally, you need to add under the "PERMISSIONS" "SSH Permissions" section a private key that is on the build server that you are using. +After adding a private key, it will show a fingerprint that should be added under the jobs that need to be run. + +Note: On the remote server you need to have the `*.pub` key file added to the `authorized_keys` file. diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 9b5477f6..d0be57c2 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -6,10 +6,13 @@ # turn echo on and error on earliest command set -ex -if [ ! -d "$HOME/$1-install" ]; then +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh - cd $HOME/ +if [ ! -d "$HOME/$1-install" ]; then + cd $HOME # init all submodules including the tools - CHIPYARD_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1 + CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR .$LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh index 00cd7217..acd038fb 100755 --- a/.circleci/build-verilator.sh +++ b/.circleci/build-verilator.sh @@ -5,11 +5,31 @@ # turn echo on and error on earliest command set -ex -cd $HOME/project +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh -cd sims/verisim +# call clean on exit +trap clean EXIT -if [ ! -d "$HOME/project/sims/verisim/verilator" ]; then - # make verilator - make verilator_install +run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR + +if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then + # set stricthostkeychecking to no (must happen before rsync) + run "echo \"Ping $SERVER\"" + + clean + + run "mkdir -p $REMOTE_CHIPYARD_DIR" + copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR + + run "make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install" + + # copy so that circleci can cache + mkdir -p $LOCAL_CHIPYARD_DIR + mkdir -p $LOCAL_VERILATOR_DIR + copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR + copy $SERVER:$REMOTE_VERILATOR_DIR/ $LOCAL_VERILATOR_DIR + + cp -r $LOCAL_VERILATOR_DIR/install/bin/* $LOCAL_VERILATOR_DIR/install/share/verilator/bin/. fi diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index ea7e30f5..630bbd08 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -5,8 +5,12 @@ # turn echo on and error on earliest command set -ex +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + # enter bhd repo -cd $HOME/project +cd $LOCAL_CHIPYARD_DIR # initialize submodules and get the hashes git submodule update --init @@ -22,7 +26,7 @@ search () { done } -submodules=("boom" "hwacha" "rocket-chip" "sifive-blocks" "testchipip") +submodules=("boom" "hwacha" "icenet" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip") dir="generators" search diff --git a/.circleci/clean-old-files.sh b/.circleci/clean-old-files.sh new file mode 100755 index 00000000..96fcf8d7 --- /dev/null +++ b/.circleci/clean-old-files.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +# clean directories that are older than 30 days +# argument is used as the directory to look in + +age () { + local AGE_SEC + local CUR_SEC + local DIFF_SEC + local SEC_PER_DAY + + SEC_PER_DAY=86400 + + CUR_SEC=$(date +%s) + AGE_SEC=$(stat -c %Y -- "$1") + DIFF_SEC=$(expr $CUR_SEC - $AGE_SEC) + + echo $(expr $DIFF_SEC / $SEC_PER_DAY) +} + +for d in $1/*/ ; do + DIR_AGE="$(age $d)" + if [ $DIR_AGE -ge 30 ]; then + echo "Deleting $d since is it $DIR_AGE old" + rm -rf $d + else + echo "Keep $d since it is $DIR_AGE old" + fi +done diff --git a/.circleci/config.yml b/.circleci/config.yml index 61e73e54..e03f2a9c 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -7,479 +7,405 @@ version: 2 jobs: commit-on-master-check: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Check commits of each submodule command: | .circleci/check-commit.sh - install-riscv-toolchain: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - run: name: Building riscv-tools toolchain command: | .circleci/build-toolchains.sh riscv-tools no_output_timeout: 120m - - save_cache: key: riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} paths: - "/home/riscvuser/riscv-tools-install" - install-esp-toolchain: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - - run: name: Building esp-tools toolchain command: | .circleci/build-toolchains.sh esp-tools no_output_timeout: 120m - - save_cache: key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} paths: - "/home/riscvuser/esp-tools-install" - install-verilator: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Build Verilator command: | .circleci/build-verilator.sh no_output_timeout: 120m - - save_cache: - key: verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + key: verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} paths: - - "/home/riscvuser/project/sims/verisim/verilator" - + - "/home/riscvuser/verilator" prepare-example: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the example subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example + command: .circleci/do-rtl-build.sh example no_output_timeout: 120m - - save_cache: key: example-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-boomexample: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh boomexample no_output_timeout: 120m - - save_cache: key: boomexample-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-boomrocketexample: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig + command: .circleci/do-rtl-build.sh boomrocketexample no_output_timeout: 120m - - save_cache: key: boomrocketexample-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-boom: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the boom subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boom + command: .circleci/do-rtl-build.sh boom no_output_timeout: 120m - - save_cache: key: boom-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-rocketchip: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the rocketchip subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip + command: .circleci/do-rtl-build.sh rocketchip no_output_timeout: 120m - - save_cache: key: rocketchip-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - - prepare-hwacha-verilog-only: + prepare-hwacha: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha verilog + command: .circleci/do-rtl-build.sh hwacha no_output_timeout: 120m - - save_cache: key: hwacha-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - - example-run-benchmark-tests: + example-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - example-{{ .Branch }}-{{ .Revision }} - + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Run example benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example - - boomexample-run-benchmark-tests: + name: Run example tests + command: .circleci/run-tests.sh example + boomexample-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - boomexample-{{ .Branch }}-{{ .Revision }} - + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Run boomexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig - - boomrocketexample-run-benchmark-tests: + name: Run boomexample tests + command: .circleci/run-tests.sh boomexample + boomrocketexample-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - boomrocketexample-{{ .Branch }}-{{ .Revision }} - + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Run boomrocketexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig - - boom-run-benchmark-tests: + name: Run boomrocketexample tests + command: .circleci/run-tests.sh boomrocketexample + boom-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - boom-{{ .Branch }}-{{ .Revision }} - + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Run boom benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boom - - rocketchip-run-benchmark-tests: + name: Run boom tests + command: .circleci/run-tests.sh boom + rocketchip-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - rocketchip-{{ .Branch }}-{{ .Revision }} - + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Run rocketchip benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=rocketchip - -# hwacha-run-benchmark-tests: -# docker: -# - image: riscvboom/riscvboom-images:0.0.5 -# environment: -# JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit -# TERM: dumb -# -# steps: -# # Checkout the code -# - checkout -# -# - run: -# name: Create hash of toolchains -# command: | -# .circleci/create-hash.sh -# -# - restore_cache: -# keys: -# - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} -# -# - restore_cache: -# keys: -# - hwacha-{{ .Branch }}-{{ .Revision }} -# -# - run: -# name: Run hwacha benchmark tests -# command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha + name: Run rocketchip tests + command: .circleci/run-tests.sh rocketchip + hwacha-run-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.10 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + steps: + - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + - restore_cache: + keys: + - hwacha-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} + - run: + name: Run hwacha tests + command: .circleci/run-tests.sh hwacha # Order and dependencies of jobs to run workflows: @@ -523,42 +449,34 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-hwacha-verilog-only: + - prepare-hwacha: requires: - - install-riscv-toolchain # TODO: Remove when esp-tools is used - install-esp-toolchain - install-verilator # Run the respective tests # Run the example tests - - example-run-benchmark-tests: + - example-run-tests: requires: - - install-riscv-toolchain - prepare-example - - boomexample-run-benchmark-tests: + - boomexample-run-tests: requires: - - install-riscv-toolchain - prepare-boomexample - - boomrocketexample-run-benchmark-tests: + - boomrocketexample-run-tests: requires: - - install-riscv-toolchain - prepare-boomrocketexample - - boom-run-benchmark-tests: + - boom-run-tests: requires: - - install-riscv-toolchain - prepare-boom - - rocketchip-run-benchmark-tests: + - rocketchip-run-tests: requires: - - install-riscv-toolchain - prepare-rocketchip -# - hwacha-run-benchmark-tests: -# requires: -# - install-riscv-toolchain # TODO: Remove when esp-tools is used -# - install-esp-toolchain -# - prepare-hwacha + - hwacha-run-tests: + requires: + - prepare-hwacha diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh index 2aff9727..84a75244 100755 --- a/.circleci/create-hash.sh +++ b/.circleci/create-hash.sh @@ -5,8 +5,12 @@ # turn echo on and error on earliest command set -ex +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + # enter bhd repo -cd $HOME/project +cd $LOCAL_CHIPYARD_DIR # get the version of riscv-tools from the git submodule hash git submodule status | grep "riscv-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/riscv-tools.hash diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh new file mode 100755 index 00000000..91b8f589 --- /dev/null +++ b/.circleci/defaults.sh @@ -0,0 +1,43 @@ +#!/bin/bash + +copy () { + rsync -avzp -e 'ssh' $1 $2 +} + +run () { + ssh -o "StrictHostKeyChecking no" -t $SERVER $@ +} + +run_script () { + ssh -o "StrictHostKeyChecking no" -t $SERVER 'bash -s' < $1 "$2" +} + +clean () { + # remove remote work dir + run "rm -rf $REMOTE_WORK_DIR" +} + +# remote variables +REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB +REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install +REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install +REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard +REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator +REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator + +# local variables (aka within the docker container) +LOCAL_CHECKOUT_DIR=$HOME/project +LOCAL_RISCV_DIR=$HOME/riscv-tools-install +LOCAL_ESP_DIR=$HOME/esp-tools-install +LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR +LOCAL_VERILATOR_DIR=$HOME/verilator +LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator + +# key value store to get the build strings +declare -A mapping +mapping["example"]="SUB_PROJECT=example" +mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig" +mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig" +mapping["boom"]="SUB_PROJECT=boom" +mapping["rocketchip"]="SUB_PROJECT=rocketchip" +mapping["hwacha"]="SUB_PROJECT=hwacha" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 51ad760b..2c7242cc 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -6,15 +6,44 @@ # turn echo on and error on earliest command set -ex -# init all submodules -cd $HOME/project +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +# call clean on exit +trap clean EXIT + +cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh -# enter the verisim directory and build the specific config -cd sims/verisim -make clean +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" -# run the particular build command -make JAVA_ARGS="-Xmx2G -Xss8M" $@ +clean -rm -rf ../../project +# copy over riscv/esp-tools, verilator, and chipyard to remote +run "mkdir -p $REMOTE_CHIPYARD_DIR" +run "mkdir -p $REMOTE_VERILATOR_DIR" +copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR +copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR + +TOOLS_DIR=$REMOTE_RISCV_DIR +LD_LIB_DIR=$REMOTE_RISCV_DIR/lib +if [ $1 = "hwacha" ]; then + TOOLS_DIR=$REMOTE_ESP_DIR + LD_LIB_DIR=$REMOTE_ESP_DIR/lib + run "mkdir -p $REMOTE_ESP_DIR" + copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR +else + run "mkdir -p $REMOTE_RISCV_DIR" + copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR +fi + +# enter the verisim directory and build the specific config on remote server +run "make -C $REMOTE_SIM_DIR clean" +run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}" +run "rm -rf $REMOTE_CHIPYARD_DIR/project" + +# copy back the final build +mkdir -p $LOCAL_CHIPYARD_DIR +copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh new file mode 100755 index 00000000..99fd42dd --- /dev/null +++ b/.circleci/run-tests.sh @@ -0,0 +1,53 @@ +#!/bin/bash + +# run the different tests + +# turn echo on and error on earliest command +set -ex + +# get remote exec variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator + +run_bmark () { + make run-bmark-tests-fast -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ +} + +run_asm () { + make run-asm-tests-fast -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ +} + +run_both () { + run_bmark $@ + run_asm $@ +} + +case $1 in + example) + run_bmark ${mapping[$1]} + ;; + boomexample) + run_bmark ${mapping[$1]} + ;; + boomrocketexample) + run_bmark ${mapping[$1]} + ;; + boom) + run_bmark ${mapping[$1]} + ;; + rocketchip) + run_bmark ${mapping[$1]} + ;; + hwacha) + export RISCV=$LOCAL_ESP_DIR + export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib + export PATH=$RISCV/bin:$PATH + make run-rv64uv-p-asm-tests -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} + ;; + *) + echo "No set of tests for $1. Did you spell it right?" + exit 1 + ;; +esac diff --git a/README.md b/README.md index e59f5af5..fd6e723f 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,8 @@ -# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master) +# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/chipyard/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master) ## Using Chipyard -To get started using Chipyard, see the documentation on the Chipyard documentation site: https://bar-project-template.readthedocs.io/en/latest/ +To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/en/latest/ ## What is Chipyard @@ -14,7 +14,7 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb ## Resources * Chipyard Website: ...TBD at a later date... -* Chipyard Documentation: https://bar-project-template.readthedocs.io/ +* Chipyard Documentation: https://chipyard.readthedocs.io/ [hwacha]:http://hwacha.org [hammer]:https://github.com/ucb-bar/hammer diff --git a/common.mk b/common.mk index 5f9d04cb..11e8c167 100644 --- a/common.mk +++ b/common.mk @@ -73,10 +73,25 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) verilog: $(sim_vsrcs) ######################################################################################### -# helper rules to run simulator +# helper rules to run simulations ######################################################################################### +.PHONY: run-binary run-fast run-binary: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + +######################################################################################### +# helper rules to run simulator as fast as possible +######################################################################################### +run-binary-fast: $(sim) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + +######################################################################################### +# helper rules to run simulator with as much debug info as possible +######################################################################################### +run-binary-debug: $(sim_debug) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + +run-fast: run-asm-tests-fast run-bmark-tests-fast ######################################################################################### # run assembly/benchmarks rules @@ -86,10 +101,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ + $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst new file mode 100644 index 00000000..6dab6378 --- /dev/null +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -0,0 +1,57 @@ +FPGA-Accelerated Simulators +============================== + +FireSim +----------------------- + +`FireSim `__ is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). +FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. +FireSim also provides additional device models to allow full-system simulation, including memory models and network models. + +FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances. +In order to simulate your Chipyard design using FireSim, if you have not +already, follow the initial EC2 setup instructions as detailed in the `FireSim +documentation `__. +Then clone Chipyard onto your FireSim manager +instance, and setup your Chipyard repository as you would normally. + +Next, initalize FireSim as library in Chipyard by running: + +.. code-block:: shell + + # At the root of your chipyard repo + ./scripts/firesim-setup.sh --fast + +``firesim-setup.sh`` initializes additional submodules and then invokes +firesim's ``build-setup.sh`` script adding ``--library`` to properly +initialize FireSim as a library submodule in chipyard. You may run +``./sims/firesim/build-setup.sh --help`` to see more options. + +Finally, source the following environment at the root of the firesim directory: + +.. code-block:: shell + + cd sims/firesim + # (Recommended) The default manager environment (includes env.sh) + source sourceme-f1-manager.sh + +`Every time you want to use FireSim with a fresh shell, you must source this sourceme.sh` + +At this point you're ready to use FireSim with Chipyard. If you're not already +familiar with FireSim, please return to the `FireSim Docs +`__, +and proceed with the rest of the tutorial. + +Current Limitations: +++++++++++++++++++++ + +FireSim integration in Chipyard is still a work in progress. Presently, you +cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, +which properly invokes MIDAS on the target RTL. + +In the interim, workaround this limitation by importing Config and Module +classes from other generator projects into FireChip. You should then be able to +refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` +variables. Note that if your target machine has I/O not provided in the default +FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need +to write a custom endpoint. diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Based-Simulators.rst deleted file mode 100644 index 1180b470..00000000 --- a/docs/Simulation/FPGA-Based-Simulators.rst +++ /dev/null @@ -1,17 +0,0 @@ -FPGA-Based Simulators -============================== - -FireSim ------------------------ - -`FireSim `__ is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). -FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. -FireSim also provides additional device models to allow full-system simulation, including memory models and network models. - -FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. -In order to simulate your Chipyard design using FireSim, you should follow the following steps: - -Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__. -Then clone your full Chipyard repository onto your Amazon EC2 FireSim manager instance. - -Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation `__. diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst deleted file mode 100644 index bc8a0dcc..00000000 --- a/docs/Simulation/Open-Source-Simulators.rst +++ /dev/null @@ -1,35 +0,0 @@ -Open Source Software RTL Simulators -============================== - -Verilator ------------------------ - -`Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. -The Chipyard framework can download, build, and execute simulations using Verilator. - -To run a simulation using Verilator, perform the following steps: - -To compile the example design, run ``make`` in the ``sims/verisim`` directory. -This will elaborate the ``DefaultRocketConfig`` in the example project. - -An executable called ``simulator-example-DefaultRocketConfig`` will be produced. -This executable is a simulator that has been compiled based on the design that was built. -You can then use this executable to run any compatible RV64 code. -For instance, to run one of the riscv-tools assembly tests. - -.. code-block:: shell - - ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple - -If you later create your own project, you can use environment variables to build an alternate configuration. - -.. code-block:: shell - - make SUB_PROJECT=yourproject - ./simulator-- ... - -If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. -This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. -An open-source vcd-capable waveform viewer is `GTKWave `__. - -Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Software-RTL-Simulators.rst similarity index 50% rename from docs/Simulation/Commercial-Simulators.rst rename to docs/Simulation/Software-RTL-Simulators.rst index 0e971d51..9df94d52 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Software-RTL-Simulators.rst @@ -1,9 +1,43 @@ -Commercial Software RTL Simulators -============================== +Software RTL Simulators +=================================== -VCS +Verilator (Open-Source) ----------------------- +`Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. +The Chipyard framework can download, build, and execute simulations using Verilator. + +To run a simulation using Verilator, perform the following steps: + +To compile the example design, run ``make`` in the ``sims/verisim`` directory. +This will elaborate the ``DefaultRocketConfig`` in the example project. + +An executable called ``simulator-example-DefaultRocketConfig`` will be produced. +This executable is a simulator that has been compiled based on the design that was built. +You can then use this executable to run any compatible RV64 code. +For instance, to run one of the riscv-tools assembly tests. + +.. code-block:: shell + + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + +If you later create your own project, you can use environment variables to build an alternate configuration. + +.. code-block:: shell + + make SUB_PROJECT=yourproject + ./simulator-- ... + +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. +This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. +An open-source vcd-capable waveform viewer is `GTKWave `__. + +Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. +Commercial Software RTL Simulators + +Synopsys VCS (License Required) +-------------------------------- + `VCS `__ is a commercial RTL simulator developed by Synopsys. It requires commercial licenses. The Chipyard framework can compile and execute simulations using VCS. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index 339960bd..50dbb57e 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,15 +1,20 @@ Simulators ======================= -Chipyard provides support and integration for multiple simulation flows, for various user levels and requirements. -In the majority of cases during a digital design development process, a simple software RTL simulation will do. -When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. -The following pages provide detailed information about the simulation possibilities within the Chipyard framework. +Chipyard supports two classes of simulation: + +#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators +#. FPGA-accelerated full-system simulation using FireSim + +Software RTL simulators of Chipyard designs run at O(1 KHz), but compile +quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run +at O(100 MHz), making them appropriate for booting an operating system and +running a complete workload, but have multi-hour compile times and poorer debug +visability. .. toctree:: :maxdepth: 2 :caption: Simulators: - Open-Source-Simulators - Commercial-Simulators - FPGA-Based-Simulators + Software-RTL-Simulators + FPGA-Accelerated-Simulators diff --git a/docs/index.rst b/docs/index.rst index 019a6991..b2fa001a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -4,7 +4,7 @@ contain the root `toctree` directive. Welcome to Chipyard's documentation! -================================= +==================================== Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. diff --git a/generators/testchipip b/generators/testchipip index 532d4a42..cd9d53c3 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 532d4a42914286548179f3893ab6349a0aedb5e3 +Subproject commit cd9d53c3611b075d0cb580e051cb3ae38864148b diff --git a/sims/vsim/.gitignore b/sims/vcs/.gitignore similarity index 100% rename from sims/vsim/.gitignore rename to sims/vcs/.gitignore diff --git a/sims/vsim/Makefile b/sims/vcs/Makefile similarity index 88% rename from sims/vsim/Makefile rename to sims/vcs/Makefile index 88aaed1e..6caf5919 100644 --- a/sims/vsim/Makefile +++ b/sims/vcs/Makefile @@ -28,6 +28,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -54,6 +56,7 @@ VCS_NONCC_OPTS = \ -error=PCWM-L \ -timescale=1ns/10ps \ -quiet \ + -q \ +rad \ +v2k \ +vcs+lic+wait \ @@ -93,17 +96,11 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp -######################################################################################### -# helper rules to run simulator with debug -######################################################################################### -run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) - ######################################################################################### # create a vcs vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - $(sim_debug) $(PERMISSIVE_ON) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< + $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< ######################################################################################### # general cleanup rule diff --git a/sims/verisim/.gitignore b/sims/verilator/.gitignore similarity index 100% rename from sims/verisim/.gitignore rename to sims/verilator/.gitignore diff --git a/sims/verisim/Makefile b/sims/verilator/Makefile similarity index 91% rename from sims/verisim/Makefile rename to sims/verilator/Makefile index 629373c8..801a521c 100644 --- a/sims/verisim/Makefile +++ b/sims/verilator/Makefile @@ -28,6 +28,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug PERMISSIVE_ON= PERMISSIVE_OFF= +WAVEFORM_FLAG=-v$(sim_out_name).vcd + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -80,19 +82,13 @@ $(sim): $(model_mk) $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk -######################################################################################### -# helper rules to run simulator with debug -######################################################################################### -run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) - ######################################################################################### # create a verisim vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - $(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $< + $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< ######################################################################################### # general cleanup rule diff --git a/sims/verisim/verilator.mk b/sims/verilator/verilator.mk similarity index 96% rename from sims/verisim/verilator.mk rename to sims/verilator/verilator.mk index 80abd869..9954aa4d 100644 --- a/sims/verisim/verilator.mk +++ b/sims/verilator/verilator.mk @@ -36,7 +36,7 @@ $(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VE $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) - wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ + wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ ######################################################################################### # verilator binary and flags diff --git a/variables.mk b/variables.mk index d9ce7781..7aefdd18 100644 --- a/variables.mk +++ b/variables.mk @@ -148,7 +148,8 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +max-cycles=$(timeout_cycles) +SIM_FLAGS ?= +VERBOSE_FLAGS ?= +verbose sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) #########################################################################################