Moved a zillion files all over the place so that everything is now
in tapeout/src in the correct directory corresponding to internal packages. Everything compiles and tests run TODO: - Figure out assembly step for MacroCompiler - Does root project matter?
This commit is contained in:
chick
406
tapeout/src/test/scala/mdf/macrolib/MacroLibSpec.scala
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406
tapeout/src/test/scala/mdf/macrolib/MacroLibSpec.scala
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@@ -0,0 +1,406 @@
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package mdf.macrolib
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import org.scalatest.flatspec.AnyFlatSpec
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import org.scalatest.matchers.should.Matchers
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import play.api.libs.json._
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object JSONUtils {
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def readStringValueMap(str: String): Option[Map[String, JsValue]] = {
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Json.parse(str) match {
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case x: JsObject => Some(x.as[Map[String, JsValue]])
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case _ => None
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}
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}
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}
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// Tests for filler macros
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class FillerMacroSpec extends AnyFlatSpec with Matchers {
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"Valid lvt macros" should "be detected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "filler cell",
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| "name": "MY_FILLER_CELL",
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| "vt": "lvt"
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe Some(FillerMacro("MY_FILLER_CELL", "lvt"))
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}
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"Valid metal macro" should "be detected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "metal filler cell",
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| "name": "METAL_FILLER_CELL",
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| "vt": "lvt"
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe Some(MetalFillerMacro("METAL_FILLER_CELL", "lvt"))
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}
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"Valid hvt macros" should "be detected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "filler cell",
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| "name": "HVT_CELL_PROP",
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| "vt": "hvt"
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe Some(FillerMacro("HVT_CELL_PROP", "hvt"))
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}
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"Empty name macros" should "be rejected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "filler cell",
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| "name": "",
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| "vt": "hvt"
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe None
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}
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"Empty vt macros" should "be rejected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "metal filler cell",
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| "name": "DEAD_CELL",
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| "vt": ""
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe None
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}
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"Missing vt macros" should "be rejected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "metal filler cell",
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| "name": "DEAD_CELL"
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe None
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}
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"Missing name macros" should "be rejected" in {
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val m = JSONUtils
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.readStringValueMap("""
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| {
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| "type": "filler cell",
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| "vt": ""
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| }
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|""".stripMargin)
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.get
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FillerMacroBase.parseJSON(m) shouldBe None
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}
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}
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// Tests for SRAM type and associates.
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class SRAMMacroSpec extends AnyFlatSpec with Matchers {
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// Simple port which can be reused in tests
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// Note: assume width=depth=simplePortConstant.
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val simplePortConstant = 1024
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def simplePort(
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postfix: String = "",
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width: Int = simplePortConstant,
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depth: Int = simplePortConstant
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): (String, MacroPort) = {
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val json = s"""
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{
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"address port name": "A_${postfix}",
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"address port polarity": "active high",
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"clock port name": "CLK_${postfix}",
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"clock port polarity": "positive edge",
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"write enable port name": "WEN_${postfix}",
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"write enable port polarity": "active high",
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"read enable port name": "REN_${postfix}",
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"read enable port polarity": "active high",
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"chip enable port name": "CEN_${postfix}",
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"chip enable port polarity": "active high",
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"output port name": "OUT_${postfix}",
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"output port polarity": "active high",
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"input port name": "IN_${postfix}",
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"input port polarity": "active high",
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"mask granularity": 1,
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"mask port name": "MASK_${postfix}",
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"mask port polarity": "active high"
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}
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"""
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val port = MacroPort(
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address = PolarizedPort(s"A_${postfix}", ActiveHigh),
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clock = Some(PolarizedPort(s"CLK_${postfix}", PositiveEdge)),
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writeEnable = Some(PolarizedPort(s"WEN_${postfix}", ActiveHigh)),
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readEnable = Some(PolarizedPort(s"REN_${postfix}", ActiveHigh)),
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chipEnable = Some(PolarizedPort(s"CEN_${postfix}", ActiveHigh)),
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output = Some(PolarizedPort(s"OUT_${postfix}", ActiveHigh)),
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input = Some(PolarizedPort(s"IN_${postfix}", ActiveHigh)),
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maskPort = Some(PolarizedPort(s"MASK_${postfix}", ActiveHigh)),
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maskGran = Some(1),
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width = Some(width),
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depth = Some(depth)
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)
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(json, port)
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}
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"Simple port" should "be valid" in {
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{
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val (json, port) = simplePort("Simple1")
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MacroPort.parseJSON(JSONUtils.readStringValueMap(json).get, simplePortConstant, simplePortConstant) shouldBe Some(
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port
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)
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}
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{
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val (json, port) = simplePort("Simple2")
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MacroPort.parseJSON(JSONUtils.readStringValueMap(json).get, simplePortConstant, simplePortConstant) shouldBe Some(
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port
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)
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}
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{
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val (json, port) = simplePort("bar")
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MacroPort.parseJSON(JSONUtils.readStringValueMap(json).get, simplePortConstant, simplePortConstant) shouldBe Some(
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port
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)
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}
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{
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val (json, port) = simplePort("")
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MacroPort.parseJSON(JSONUtils.readStringValueMap(json).get, simplePortConstant, simplePortConstant) shouldBe Some(
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port
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)
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}
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}
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"Simple SRAM macro" should "be detected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "SRAMS_R_US",
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"width": 2048,
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"depth": "4096",
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"family": "1rw",
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"ports": [
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${json}
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]
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe Some(
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SRAMMacro("SRAMS_R_US", width = 2048, depth = 4096, family = "1rw", ports = List(port), extraPorts = List())
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)
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}
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"Non-power-of-two width & depth SRAM macro" should "be detected" in {
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val (json, port) = simplePort("", 1234, 8888)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "SRAMS_R_US",
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"width": 1234,
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"depth": "8888",
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"family": "1rw",
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"ports": [
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${json}
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]
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe Some(
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SRAMMacro("SRAMS_R_US", width = 1234, depth = 8888, family = "1rw", ports = List(port), extraPorts = List())
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)
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}
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"Minimal memory port" should "be detected" in {
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val (json, port) = simplePort("_A", 64, 1024)
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val port2 = MacroPort(
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address = PolarizedPort("A_B", ActiveHigh),
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clock = Some(PolarizedPort("CLK_B", PositiveEdge)),
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writeEnable = Some(PolarizedPort("WEN_B", ActiveHigh)),
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readEnable = None,
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chipEnable = None,
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output = Some(PolarizedPort("OUT_B", ActiveHigh)),
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input = Some(PolarizedPort("IN_B", ActiveHigh)),
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maskPort = None,
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maskGran = None,
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width = Some(64),
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depth = Some(1024)
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)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "SRAMS_R_US",
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"width": 64,
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"depth": "1024",
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"family": "2rw",
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"ports": [
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${json},
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{
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"address port name": "A_B",
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"address port polarity": "active high",
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"clock port name": "CLK_B",
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"clock port polarity": "positive edge",
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"write enable port name": "WEN_B",
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"write enable port polarity": "active high",
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"output port name": "OUT_B",
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"output port polarity": "active high",
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"input port name": "IN_B",
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"input port polarity": "active high"
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}
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]
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe Some(
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SRAMMacro("SRAMS_R_US", width = 64, depth = 1024, family = "2rw", ports = List(port, port2), extraPorts = List())
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)
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}
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"Extra ports" should "be detected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "GOT_EXTRA",
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"width": 2048,
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"depth": "4096",
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"family": "1rw",
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"ports": [
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${json}
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],
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"extra ports": [
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{
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"name": "TIE_DIE",
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"width": 1,
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"type": "constant",
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"value": 1
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},
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{
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"name": "TIE_MOO",
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"width": 4,
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"type": "constant",
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"value": 0
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}
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]
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe Some(
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SRAMMacro(
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"GOT_EXTRA",
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width = 2048,
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depth = 4096,
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family = "1rw",
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ports = List(port),
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extraPorts = List(
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MacroExtraPort(
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name = "TIE_DIE",
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width = 1,
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portType = Constant,
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value = 1
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),
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MacroExtraPort(
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name = "TIE_MOO",
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width = 4,
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portType = Constant,
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value = 0
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)
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)
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)
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)
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}
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"Invalid port" should "be rejected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "SRAMS_R_US",
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"width": 2048,
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"depth": "4096",
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"family": "1rw",
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"ports": [
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{
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"address port name": "missing_polarity",
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"output port name": "missing_clock"
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}
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]
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe None
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}
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"No ports" should "be rejected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "SRAMS_R_US",
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"width": 2048,
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"depth": "4096",
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"family": "1rw"
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe None
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}
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"No family and ports" should "be rejected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "SRAMS_R_US",
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"width": 2048,
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"depth": "4096"
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe None
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}
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"String width" should "be rejected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "BAD_BAD_SRAM",
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"width": "wide",
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"depth": "4096"
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe None
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}
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"String depth" should "be rejected" in {
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val (json, port) = simplePort("", 2048, 4096)
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val m = JSONUtils
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.readStringValueMap(s"""
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{
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"type": "sram",
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"name": "BAD_BAD_SRAM",
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"width": 512,
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"depth": "octopus_under_the_sea"
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}
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""")
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.get
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SRAMMacro.parseJSON(m) shouldBe None
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}
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}
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Reference in New Issue
Block a user