From 7f5d8c8dba9600a3ab47fae955802c1cf8c96290 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 24 Feb 2021 13:05:14 -0800 Subject: [PATCH 01/68] Update frequency selection related comments --- generators/firechip/src/main/scala/TargetConfigs.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 92cd02c3..ece2546b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -68,8 +68,10 @@ class WithFireSimConfigTweaks extends Config( new WithFireSimSimpleClocks ++ // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source new WithBootROM ++ - // Optional*: Removing this will require adjusting the UART baud rate and - // potential target-software changes to properly capture UART output + // Optional: This sets the default frequency for all buses in the system to 3.2 GHz + // (since unspecified bus frequencies will use the pbus frequency) + // This frequency selection matches FireSim's legacy selection and is required + // to support 200Gb NIC performance. You may select a smaller value. new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ // Optional: These three configs put the DRAM memory system in it's own clock domian. // Removing the first config will result in the FASED timing model running @@ -93,7 +95,7 @@ class WithFireSimConfigTweaks extends Config( new testchipip.WithDefaultSerialTL ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ - // Required*: Scale default baud rate with periphery bus frequency + // Optional: Set a UART baudrate (this selection matches FireSim's historical value) new chipyard.config.WithUART(BigInt(3686400L)) ++ // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock) new chipyard.config.WithNoDebug From 6eab7c813eee5b7fb308c27498e213561fcb3b85 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 29 Mar 2021 19:36:06 +0000 Subject: [PATCH 02/68] Bump pygments from 2.2.0 to 2.7.4 in /docs Bumps [pygments](https://github.com/pygments/pygments) from 2.2.0 to 2.7.4. - [Release notes](https://github.com/pygments/pygments/releases) - [Changelog](https://github.com/pygments/pygments/blob/master/CHANGES) - [Commits](https://github.com/pygments/pygments/compare/2.2.0...2.7.4) Signed-off-by: dependabot[bot] --- docs/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index 4b1565b3..0407da5e 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,4 +1,4 @@ Sphinx==1.8.5 -Pygments==2.2.0 +Pygments==2.7.4 sphinx-autobuild sphinx_rtd_theme==0.2.5b1 From c061ea0ac971a5cba7da6023b65e74f48f589580 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 30 Mar 2021 01:45:34 -0700 Subject: [PATCH 03/68] Bump testchipip | Add custom boot pin --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 ++ generators/chipyard/src/main/scala/HarnessBinders.scala | 6 ++++++ generators/chipyard/src/main/scala/IOBinders.scala | 7 +++++++ .../chipyard/src/main/scala/config/AbstractConfig.scala | 2 ++ generators/testchipip | 2 +- 5 files changed, 18 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 7fd682d2..3407b4da 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,6 +13,8 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem + with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin + with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index da497a54..c1ec2bda 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -321,3 +321,9 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({ ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } } }) + +class WithTieOffCustomBootPin extends OverrideHarnessBinder({ + (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { + ports.foreach(_ := false.B) + } +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 5d153834..dd74e960 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -372,6 +372,13 @@ class WithTraceIOPunchthrough extends OverrideIOBinder({ } }) +class WithCustomBootPin extends OverrideIOBinder({ + (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true) + (Seq(port), cells) + }).getOrElse((Nil, Nil)) +}) class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index da84bd05..6660d159 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -21,6 +21,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present + new chipyard.harness.WithTieOffCustomBootPin ++ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through @@ -37,6 +38,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithSPIIOCells ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ + new chipyard.iobinders.WithCustomBootPin ++ new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new chipyard.config.WithBootROM ++ // use default bootrom diff --git a/generators/testchipip b/generators/testchipip index fd7760e2..a973fdd6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit fd7760e2862661bf6277acfeeb42644797e876d0 +Subproject commit a973fdd67f650555fdf64e2d904eba9a0af691a3 From bbaebcd596c18def77c59f4c963fa52189c04d0b Mon Sep 17 00:00:00 2001 From: Anoop Date: Wed, 31 Mar 2021 17:28:24 +0530 Subject: [PATCH 04/68] Update barstools.rst Added info about adding our own sram-macros cache --- docs/Tools/Barstools.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 6bd8f036..a36a29b1 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -24,7 +24,7 @@ A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, wh Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route. The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Barstools:Barstools` scala package. -MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. +MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. You may wish to create a cache of your available SRAM macros either manually, or via a script. An reference script for creating a JSON of your SRAM macros is in the `asap7 technology library folder `__; the expected JSON format is `here `_. Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Barstools:SRAM MDF Fields`). Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file. This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying. From 709c6bb36573c350a90568d1102ae9879ab23019 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 31 Mar 2021 09:19:29 -0700 Subject: [PATCH 05/68] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index a973fdd6..c50a0e2e 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a973fdd67f650555fdf64e2d904eba9a0af691a3 +Subproject commit c50a0e2e32d71f4f956c8a616a5ec2f7e31792fb From a7befc8c5c45f0c3a77fe660e1b96a7ba2991d61 Mon Sep 17 00:00:00 2001 From: Anoop Date: Wed, 31 Mar 2021 22:19:49 +0530 Subject: [PATCH 06/68] Updated barstools.rst after review-1 Edits after review-1 --- docs/Tools/Barstools.rst | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index a36a29b1..d8dd0427 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -24,13 +24,14 @@ A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, wh Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route. The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Barstools:Barstools` scala package. -MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. You may wish to create a cache of your available SRAM macros either manually, or via a script. An reference script for creating a JSON of your SRAM macros is in the `asap7 technology library folder `__; the expected JSON format is `here `_. +MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Barstools:SRAM MDF Fields`). Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file. This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying. Arraying can be done in both width and depth, as well as to solve masking constraints. For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth. If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration. +You may wish to create a cache of your available SRAM macros either manually, or via a script. A reference script for creating a JSON of your SRAM macros is in the asap7 technology library` folder `__. For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`Tools/Barstools:SRAM MDF Fields` section. The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``. @@ -73,7 +74,6 @@ Likewise, the ``--force-compile [mem]`` option allows the user to force MacroCom SRAM MDF Fields +++++++++++++++ - Technology SRAM macros described in MDF can be defined at three levels of detail. A single instance can be defined with the `SRAMMacro` format. A group of instances that share the number and type of ports but vary in width and depth can be defined with the `SRAMGroup` format. @@ -82,12 +82,14 @@ A set of groups of SRAMs that can be generated together from a single source lik At the most concrete level the `SRAMMAcro` defines a particular instance of an SRAM. That includes its functional attributes such as its width, depth, and number of access ports. These ports can be read, write, or read and write ports, and the instance can have any number. -In order to correctly map to these functional ports to the physical instance each port is described in a list of sub-structures, in the parent instance's structure. +In order to correctly map these functional ports to the physical instance, each port is described in a list of sub-structures, in the parent instance's structure. Each port is only required to have an address and data field, but can have many other optional fields. -These optional fields include a clock, write enable, read enable, chip enable, mask. +These optional fields include a clock, write enable, read enable, chip enable, mask and its granularity. The mask field can have a different granularity than the data field, e.g. it could be a bit mask or a byte mask. Each field must also specify its polarity, whether it is active high or active low. +The specific JSON file format described above is `here `_. A reference cache of SRAMs from the nangate45 technology library is `available here `_. + In addition to these functional descriptions of the SRAM there are also other fields that specify physical/implementation characteristics. These include the threshold voltage, the mux factor, as well as a list of extra non-functional ports. From 3b26d6a9f99534d589d82d9b91b28d1b96ae9024 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 31 Mar 2021 17:04:42 -0700 Subject: [PATCH 07/68] Bump requirements to get newer Git version (for CI) --- scripts/ubuntu-req.sh | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index b33a6649..5f618b71 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -3,7 +3,7 @@ set -ex sudo apt-get install -y build-essential bison flex -sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre +sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim default-jdk default-jre # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add @@ -12,7 +12,7 @@ sudo apt-get install -y sbt sudo apt-get install -y texinfo gengetopt sudo apt-get install -y libexpat1-dev libusb-dev libncurses5-dev cmake # deps for poky -sudo apt-get install -y python3.6 patch diffstat texi2html texinfo subversion chrpath git wget +sudo apt-get install -y python3.6 patch diffstat texi2html texinfo subversion chrpath wget # deps for qemu sudo apt-get install -y libgtk-3-dev gettext # deps for firemarshal @@ -20,6 +20,10 @@ sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat c # install DTC sudo apt-get install -y device-tree-compiler sudo apt-get install -y python +# install git >= 2.17 +sudo add-apt-repository ppa:git-core/ppa -y +sudo apt-get update +sudo apt-get install git -y # install verilator git clone http://git.veripool.org/git/verilator From ab57b7d2edaad950b0f2b99a633341fa9833274b Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 31 Mar 2021 19:00:59 -0700 Subject: [PATCH 08/68] Enable add-apt-repo --- scripts/ubuntu-req.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index 5f618b71..4889dc48 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -2,7 +2,7 @@ set -ex -sudo apt-get install -y build-essential bison flex +sudo apt-get install -y build-essential bison flex software-properties-common sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim default-jdk default-jre # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list From 4ab2228926c7af958ed6ccd179fb90b67c52df8e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 31 Mar 2021 19:15:34 -0700 Subject: [PATCH 09/68] Bump CI image --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 9c6e9f80..bdd90443 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: ucbbar/chipyard-ci-image:9c650dea + - image: ucbbar/chipyard-ci-image:ab57b7d environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit From f334d5799f881cec3df9c8b4d6824d4f6c7d5023 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 1 Apr 2021 16:21:16 -0700 Subject: [PATCH 10/68] Support 30MiB payloads - VCU118 FPGA --- fpga/src/main/resources/vcu118/sdboot/sd.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index 47c87d5f..5f465ef6 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -8,10 +8,12 @@ #define DEBUG #include "kprintf.h" -#define MAX_CORES 8 - -// A sector is 512 bytes, so ((1 << 11) * 512) = 1 MiB -#define PAYLOAD_SIZE (16 << 11) +// Total payload in B +#define PAYLOAD_SIZE_B (30 << 20) // default: 30MiB +// A sector is 512 bytes, so (1 << 11) * 512B = 1 MiB +#define SECTOR_SIZE_B 512 +// Payload size in # of sectors +#define PAYLOAD_SIZE (PAYLOAD_SIZE_B / SECTOR_SIZE_B) // The sector at which the BBL partition starts #define BBL_PARTITION_START_SECTOR 34 @@ -168,9 +170,12 @@ static int copy(void) int rc = 0; dputs("CMD18"); + + kprintf("LOADING 0x%lxB PAYLOAD\r\n", PAYLOAD_SIZE_B); kprintf("LOADING "); - // John: Let's go slow until we get this working + // TODO: Can this be sped up? + // John Wright: Let's go slow until we get this working //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { @@ -182,7 +187,7 @@ static int copy(void) long n; crc = 0; - n = 512; + n = SECTOR_SIZE_B; while (sd_dummy() != 0xFE); do { uint8_t x = sd_dummy(); From 5a41c5d9ac20414c0071997e803ede13540f7fd9 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 1 Apr 2021 16:21:44 -0700 Subject: [PATCH 11/68] Use multi-clock config. frags to determine VCU118 clk freq --- fpga/src/main/scala/vcu118/Configs.scala | 15 +++++++-------- fpga/src/main/scala/vcu118/TestHarness.scala | 7 +++---- .../src/main/scala/config/AbstractConfig.scala | 1 - 3 files changed, 10 insertions(+), 13 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 8b17aa98..18f04de4 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,7 +17,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem} +import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -26,11 +26,10 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) - case DTSTimebase => BigInt(1000000) + case DTSTimebase => BigInt((1e6).toLong) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for sdboot - val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 + val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" require (make.! == 0, "Failed to build bootrom") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") @@ -52,7 +51,9 @@ class WithVCU118Tweaks extends Config( new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ + new WithFPGAFrequency(100) // default 100MHz freq +) class RocketVCU118Config extends Config( new WithVCU118Tweaks ++ @@ -64,9 +65,7 @@ class BoomVCU118Config extends Config( new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) -class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { - case FPGAFrequencyKey => MHz -}) +class WithFPGAFrequency(fMHz: Double) extends chipyard.config.WithPeripheryBusFrequency(fMHz) class WithFPGAFreq25MHz extends WithFPGAFrequency(25) class WithFPGAFreq50MHz extends WithFPGAFrequency(50) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 45afe7f7..64ad3deb 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,12 +17,10 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} -case object FPGAFrequencyKey extends Field[Double](100.0) - class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { def dp = designParameters @@ -55,7 +53,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S harnessSysPLL := sysClkNode // create and connect to the dutClock - val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + println(s"VCU118 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz") + val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey)) val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index da84bd05..71526d71 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -45,7 +45,6 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) - new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) From 3a52b709dbf691ed8864fc845d41aa7ecf8f3987 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Apr 2021 09:39:46 -0700 Subject: [PATCH 12/68] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index c50a0e2e..bddf17c2 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c50a0e2e32d71f4f956c8a616a5ec2f7e31792fb +Subproject commit bddf17c28dc43e5ed89ffa58bceda9bee64ddde6 From 2cfd930a32a3589714486a95550eedfc7cadeb20 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 2 Apr 2021 16:43:23 -0700 Subject: [PATCH 13/68] Bump FireMarshal for prototype targets --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index aa8e6aa8..0ada8d84 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit aa8e6aa8714d46b74917ebaa91333f5727e34599 +Subproject commit 0ada8d84e2b2826a70a1ecf9dde01426d52d2475 From be13781a1c9711bb392f42491f569e0022b0ab17 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 2 Apr 2021 16:43:59 -0700 Subject: [PATCH 14/68] Set both MBUS/PBUS in configs | Add simple check for correct clocks --- fpga/src/main/scala/vcu118/Configs.scala | 8 +++++++- fpga/src/main/scala/vcu118/TestHarness.scala | 9 ++++++++- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 18f04de4..9da3ae1e 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -40,12 +40,15 @@ class WithSystemModifications extends Config((site, here, up) => { // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( + // harness binders new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ + // io binders new WithUARTIOPassthrough ++ new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ + // other configuration new WithDefaultPeripherals ++ new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size @@ -65,7 +68,10 @@ class BoomVCU118Config extends Config( new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) -class WithFPGAFrequency(fMHz: Double) extends chipyard.config.WithPeripheryBusFrequency(fMHz) +class WithFPGAFrequency(fMHz: Double) extends Config( + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithMemoryBusFrequency(fMHz) +) class WithFPGAFreq25MHz extends WithFPGAFrequency(25) class WithFPGAFreq50MHz extends WithFPGAFrequency(50) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 64ad3deb..33161b68 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,7 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey, HasReferenceClockFreq} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -135,4 +135,11 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod _outer.topDesign match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } + + // check the top-level reference clock is equal to the default + // non-exhaustive since you need all ChipTop clocks to equal the default + _outer.topDesign match { + case d: HasReferenceClockFreq => require(d.refClockFreqMHz == p(DefaultClockFrequencyKey)) + case _ => + } } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 71526d71..da84bd05 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -45,6 +45,7 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) + new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) From 985faa4c8e9608a80889afdd5a838a3fed9e8470 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 3 Apr 2021 12:55:27 -0700 Subject: [PATCH 15/68] Small comment updates + cleanup --- fpga/src/main/resources/vcu118/sdboot/sd.c | 5 ++--- fpga/src/main/scala/vcu118/Configs.scala | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index 5f465ef6..f1bdb61e 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -171,11 +171,10 @@ static int copy(void) dputs("CMD18"); - kprintf("LOADING 0x%lxB PAYLOAD\r\n", PAYLOAD_SIZE_B); + kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B); kprintf("LOADING "); - // TODO: Can this be sped up? - // John Wright: Let's go slow until we get this working + // TODO: Speed up SPI freq. (breaks between these two values) //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 9da3ae1e..47a22dcf 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -69,7 +69,7 @@ class BoomVCU118Config extends Config( new chipyard.MegaBoomConfig) class WithFPGAFrequency(fMHz: Double) extends Config( - new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ + new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. new chipyard.config.WithMemoryBusFrequency(fMHz) ) From 565ef2eb3cbf0265a9fe36d0e497af12612b8f0d Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 3 Apr 2021 12:57:10 -0700 Subject: [PATCH 16/68] First commit of docs [ci skip] --- docs/Prototyping/VCU118.rst | 77 +++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 7f8f2cb9..0ad7bed7 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -58,3 +58,80 @@ The TSI Host Widget is used to interact with the DUT from the prototype over a S .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables. + +Running Linux with SDCard Setup +------------------------------- + +Both the bringup and normal VCU118 platforms are setup to boot Linux loaded from the SPI SDCard. + +Building Linux with FireMarshal +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To build Linux that will run on the VCU118 prototype, we will use the FireMarshal platform. +To understand FireMarshal in more depth, refer to it's documentation. + +1. Setup FireMarshal +2. Switch the FireMarshal "board" to target the prototype platform using ``marshal-config.yaml`` + +``` + echo "board-dir : \'boards/prototype\' > PATH_TO_FIREMARSHAL/marshal-config.yaml +``` + +This should allow you to use the ``br-base.json`` workload built for the prototype platform (includes GPIO/SPI drivers). + +3. Run ``./marshal -v -d build br-base.json`` to build the workload with initramfs. + +4. Install the workload ``./marshal -v -d install -t prototype br-base.json``. This will flatten the binary. + +.. note:: Feel free to modify and build off the `br-base.json` using normal FireMarshal functionality. + +Setting up the SDCard +~~~~~~~~~~~~~~~~~~~~~ + +The following instructions are for Linux but you can follow a similar set of steps on Mac (using `gpt`). + +Linux Instructions +================== + +Use `gdisk` to put the binary on the SDCard. +The following steps use `/dev/sdc` as the path to the SD card (replace with your own path). + +1. Wipe the GPT on the card. + +`sudo gdisk /dev/sdc` + +2. Use the `z` command to zap everything. + +`sudo gdisk /dev/sdc` + +3. Change the default partition alignment to `1` so you can write to sector `34`. +Do this with the `l` command. + +4. Then create the new GPT with `o`. Click yes on all the prompts. + +5. Create a 512MiB partition to store the Linux payload (note this can be smaller but it must be larger than the size of the Linux payload). +Use `n` and select sector 34, with size `+1048576`. +For the type search for the `apfs` type and use the hex number given. + +6. Create a second partition to store any other files with the rest of the SDCard. +Use `n` and use the defaults for starting sector and overall size. +For the type search for the `hfs` and use the hex number given. + +7. Write the changes using `w`. + +8. Setup the filesystem on the 2nd partition using the following command: + +`sudo mkfs.hfs -v "Prototype Data" /dev/sdc2` + +Note that `sdc2` is used since it points to the 2nd partition. + +Transfer Linux to the SDCard +============================ + +Finally transfer the `-flat` binary generated by FireMarshal to the sdcard: + +`sudo dd if=/br-base-bin-nodisk-flat of=/dev/sdc1` + +Note that `sdc1` points to the 1st partition. + +Additionally at this point you can mount the 2nd partition, add files, and mount that on the Linux on the prototype. From e159c4f6a7087b55e9e4dd1789d04109f05c58bd Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 3 Apr 2021 13:48:58 -0700 Subject: [PATCH 17/68] Cleanup docs for Linux on VCU118 --- docs/Prototyping/VCU118.rst | 110 ++++++++++++++++++++++-------------- 1 file changed, 68 insertions(+), 42 deletions(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 0ad7bed7..ee343d2d 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -59,79 +59,105 @@ The TSI Host Widget is used to interact with the DUT from the prototype over a S For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables. -Running Linux with SDCard Setup -------------------------------- +Running Linux with Basic and Bringup Platforms +---------------------------------------------- -Both the bringup and normal VCU118 platforms are setup to boot Linux loaded from the SPI SDCard. +As mentioned above, the default VCU118 harness is setup with a UART and a SPI SDCard. +These are utilized to both interact with the DUT (with the UART) and load in Linux (with the SDCard). +The following steps describe how to build and run buildroot Linux on the prototype platform. Building Linux with FireMarshal ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -To build Linux that will run on the VCU118 prototype, we will use the FireMarshal platform. -To understand FireMarshal in more depth, refer to it's documentation. +Since the prototype does not have a block device we build Linux with the rootfs built into the binary (otherwise known as "initramfs" or "nodisk" version of Linux). +To make building this type of Linux binary easy, we will use the FireMarshal platform (see :ref:`fire-marshal` for more information). -1. Setup FireMarshal -2. Switch the FireMarshal "board" to target the prototype platform using ``marshal-config.yaml`` +1. Setup FireMarshal (see :ref:`fire-marshal` on the initial setup). +2. By default FireMarshal is setup to work with FireSim. + Instead we want to target the prototype platform. + This is done by switching the FireMarshal "board" from "firechip" to "prototype" using ``marshal-config.yaml``: -``` - echo "board-dir : \'boards/prototype\' > PATH_TO_FIREMARSHAL/marshal-config.yaml -``` +.. code-block:: shell -This should allow you to use the ``br-base.json`` workload built for the prototype platform (includes GPIO/SPI drivers). + echo "board-dir : 'boards/prototype'" > $PATH_TO_FIREMARSHAL/marshal-config.yaml -3. Run ``./marshal -v -d build br-base.json`` to build the workload with initramfs. +.. Note:: Refer to the FireMarshal docs on more ways to set the board differently through environment variables and more. -4. Install the workload ``./marshal -v -d install -t prototype br-base.json``. This will flatten the binary. +3. Next build the workload (a.k.a buildroot Linux) with nodisk with FireMarshal. + For the rest of these steps we will assume you are using the base ``br-base.json`` workload. + This workload has basic support for GPIO and SPI drivers but you can build off it in different workloads (refer to FireMarshal docs on workload inheritance). -.. note:: Feel free to modify and build off the `br-base.json` using normal FireMarshal functionality. +.. code-block:: shell + + ./marshal -v -d build br-base.json # here the -d indicates --nodisk or initramfs + +.. Note:: Using the "board" FireMarshal functionality allows any child workload depending on ``br-base.json`` to use the "prototype" ``br-base.json`` rather than the FireChip version. + Thus you can re-use existing workloads that depend on ``br-base.json`` on the prototype platform by just changing the "board"! + +4. The last step to generate the proper binary is to flatten it. + This is done by using FireMarshal's install feature and will produce a ``*-flat`` binary in the ``$PATH_TO_FIREMARSHAL/images`` directory (in our case ``br-base-bin-nodisk-flat``). + +.. code-block:: shell + + ./marshal -v -d install -t prototype br-base.json Setting up the SDCard ~~~~~~~~~~~~~~~~~~~~~ -The following instructions are for Linux but you can follow a similar set of steps on Mac (using `gpt`). +These instructions assume that you have a spare uSDCard that can be loaded with Linux and other files using two partitions. +The 1st partition will be used to store the Linux binary (created with FireMarshal or other means) while the 2nd partition will be used to store miscellaneous files. +Additionally, these instructions assume you are using Linux with ``sudo`` privileges and ``gdisk`` but you can follow a similar set of steps on Mac (using ``gpt`` or another similar program). -Linux Instructions -================== +1. Wipe the GPT on the card using ``gdisk``. + Use the `z` command to zap everything. + For rest of these instructions, we assume the SDCard path is ``/dev/sdc`` (replace this with the path to your SDCard). -Use `gdisk` to put the binary on the SDCard. -The following steps use `/dev/sdc` as the path to the SD card (replace with your own path). +.. code-block:: shell -1. Wipe the GPT on the card. + sudo gdisk /dev/sdc -`sudo gdisk /dev/sdc` +2. The VCU118 bootrom assumes that the Linux binary to load into memory will be located on sector 34 of the SDCard. + Change the default partition alignment to `1` so you can write to sector `34`. + Do this with the `l` command. -2. Use the `z` command to zap everything. +3. Create the new GPT with `o`. Click yes on all the prompts. -`sudo gdisk /dev/sdc` +4. Create a 512MiB partition to store the Linux binary (this can be smaller but it must be larger than the size of the Linux binary). + Use `n` and select sector 34, with size `+1048576` (corresponding to 512MiB). + For the type search for the `apfs` type and use the hex number given. -3. Change the default partition alignment to `1` so you can write to sector `34`. -Do this with the `l` command. +5. Create a second partition to store any other files with the rest of the SDCard. + Use `n` and use the defaults for starting sector and overall size (expand the 2nd partition to the rest of the SDCard space). + For the type search for the `hfs` and use the hex number given. -4. Then create the new GPT with `o`. Click yes on all the prompts. +6. Write the changes using `w`. -5. Create a 512MiB partition to store the Linux payload (note this can be smaller but it must be larger than the size of the Linux payload). -Use `n` and select sector 34, with size `+1048576`. -For the type search for the `apfs` type and use the hex number given. +7. Setup the filesystem on the 2nd partition. + Note that the ``/dev/sdc2`` points to the 2nd partition. + Use the following command: -6. Create a second partition to store any other files with the rest of the SDCard. -Use `n` and use the defaults for starting sector and overall size. -For the type search for the `hfs` and use the hex number given. +.. code-block:: shell -7. Write the changes using `w`. + sudo mkfs.hfs -v "PrototypeData" /dev/sdc2 -8. Setup the filesystem on the 2nd partition using the following command: +Transfer and Run Linux from the SDCard +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -`sudo mkfs.hfs -v "Prototype Data" /dev/sdc2` +After you have a Linux boot binary and the SDCard is setup properly (1st partition at sector 34), you can transfer the binary to the 1st SDCard partition. +In this example, we generated a ``br-base-bin-nodisk-flat`` from FireMarshal and we will load it using ``dd``. +Note that ``sdc1`` points to the 1st partition (remember to change the ``sdc`` to your own SDCard path). -Note that `sdc2` is used since it points to the 2nd partition. +.. code-block:: shell -Transfer Linux to the SDCard -============================ + sudo dd if=$PATH_TO_FIREMARSHAL/br-base-bin-nodisk-flat of=/dev/sdc1 -Finally transfer the `-flat` binary generated by FireMarshal to the sdcard: +If you want to add files to the 2nd partition, you can also do this now. -`sudo dd if=/br-base-bin-nodisk-flat of=/dev/sdc1` +After loading the SDCard with Linux and potentially other files, you can program the FPGA and plug in the SDCard. +To interact with Linux via the UART console, you can connect to the serial port (in this case called ``ttyUSB1``) using something like ``screen``: -Note that `sdc1` points to the 1st partition. +.. code-block:: shell -Additionally at this point you can mount the 2nd partition, add files, and mount that on the Linux on the prototype. + screen -S FPGA_UART_CONSOLE /dev/ttyUSB1 115200 + +Once connected you should see the binary being loaded as well as Linux output (in some cases you might need to reset the DUT). From a401861f5b9d650f3eab89f37d2516fc12bd9d93 Mon Sep 17 00:00:00 2001 From: Anoop Date: Tue, 6 Apr 2021 10:02:47 +0530 Subject: [PATCH 18/68] Update Barstools.rst --- docs/Tools/Barstools.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 0ebf9e70..fa4176c4 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -31,7 +31,7 @@ This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60 Arraying can be done in both width and depth, as well as to solve masking constraints. For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth. If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration. -You may wish to create a cache of your available SRAM macros either manually, or via a script. A reference script for creating a JSON of your SRAM macros is in the asap7 technology library` folder `__. +You may wish to create a cache of your available SRAM macros either manually, or via a script. A reference script for creating a JSON of your SRAM macros is in the `asap7 technology library folder `__. For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`Tools/Barstools:SRAM MDF Fields` section. The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``. From ffd312f6ea1c904a56ddffeb016c8c55fa2b2bae Mon Sep 17 00:00:00 2001 From: Anoop Date: Tue, 6 Apr 2021 10:10:39 +0530 Subject: [PATCH 19/68] conflict resolution --- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index dd2e2bcc..43fea874 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -77,7 +77,7 @@ class WithFireSimDesignTweaks extends Config( new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ - // Optional: Set a UART baudrate (this selection matches FireSim's historical value) + // Required*: Scale default baud rate with periphery bus frequency new chipyard.config.WithUART(BigInt(3686400L)) ++ // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock) new chipyard.config.WithNoDebug From 436c235b1710839b04d0acd30e1250db7ba40164 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 6 Apr 2021 12:24:07 -0700 Subject: [PATCH 20/68] Bump FireMarshal --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 0ada8d84..8d9f7184 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 0ada8d84e2b2826a70a1ecf9dde01426d52d2475 +Subproject commit 8d9f71841e2215292c6fef663a98d4715998c047 From b0d69eada6e7b9c7deded3789a86d5a32c37c3f9 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 6 Apr 2021 14:32:41 -0700 Subject: [PATCH 21/68] Workaround docutils issue in doc generation Need this until the following is fixed: https://github.com/sphinx-doc/sphinx/issues/9063 --- docs/requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/requirements.txt b/docs/requirements.txt index 4b1565b3..bbd41a71 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -2,3 +2,4 @@ Sphinx==1.8.5 Pygments==2.2.0 sphinx-autobuild sphinx_rtd_theme==0.2.5b1 +docutils==0.16 From 8ed61d6a7ddce8a9c53ba34737177ce2a8802c9c Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 7 Apr 2021 12:13:41 -0700 Subject: [PATCH 22/68] Bump FireMarshal --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 8d9f7184..22f9101d 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 8d9f71841e2215292c6fef663a98d4715998c047 +Subproject commit 22f9101d456f36d9580bd3327a1613e39812d06d From 358b97b83225dfa338ca090d74ff58da5e0b4e8e Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Wed, 7 Apr 2021 18:56:10 -0400 Subject: [PATCH 23/68] Bump the spec workload to get the marshal overhaul --- software/spec2017 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/spec2017 b/software/spec2017 index 8f2812be..83e33110 160000 --- a/software/spec2017 +++ b/software/spec2017 @@ -1 +1 @@ -Subproject commit 8f2812bebc15ae36f15cb8b80f4b50aa7d342b46 +Subproject commit 83e33110472c47aaa762257ed7c053ff1278834c From dae8c12c600bcc46163c6bcf852679b45ce6e33c Mon Sep 17 00:00:00 2001 From: Alfonso Rodriguez Date: Fri, 9 Apr 2021 20:12:19 +0200 Subject: [PATCH 24/68] Ensure proper alignment with 'CacheBlockBytes' in charcount test --- tests/charcount.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/charcount.c b/tests/charcount.c index f8b3641b..6a3d2744 100644 --- a/tests/charcount.c +++ b/tests/charcount.c @@ -1,6 +1,6 @@ #include "rocc.h" -char string[64] = "The quick brown fox jumped over the lazy dog"; +char string[64] __attribute__ ((aligned (64))) = "The quick brown fox jumped over the lazy dog"; static inline unsigned long count_chars(char *start, char needle) { From b152bbd0d4a1b092717762e281310fe9603eb4c3 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 12 Apr 2021 11:02:23 -0700 Subject: [PATCH 25/68] Update grammer issues a bit --- docs/Prototyping/VCU118.rst | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index ee343d2d..1fb4fcf9 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -69,12 +69,12 @@ The following steps describe how to build and run buildroot Linux on the prototy Building Linux with FireMarshal ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Since the prototype does not have a block device we build Linux with the rootfs built into the binary (otherwise known as "initramfs" or "nodisk" version of Linux). +Since the prototype does not have a block device, we build Linux with the rootfs built into the binary (otherwise known as "initramfs" or "nodisk" version of Linux). To make building this type of Linux binary easy, we will use the FireMarshal platform (see :ref:`fire-marshal` for more information). 1. Setup FireMarshal (see :ref:`fire-marshal` on the initial setup). -2. By default FireMarshal is setup to work with FireSim. - Instead we want to target the prototype platform. +2. By default, FireMarshal is setup to work with FireSim. + Instead, we want to target the prototype platform. This is done by switching the FireMarshal "board" from "firechip" to "prototype" using ``marshal-config.yaml``: .. code-block:: shell @@ -83,8 +83,8 @@ To make building this type of Linux binary easy, we will use the FireMarshal pla .. Note:: Refer to the FireMarshal docs on more ways to set the board differently through environment variables and more. -3. Next build the workload (a.k.a buildroot Linux) with nodisk with FireMarshal. - For the rest of these steps we will assume you are using the base ``br-base.json`` workload. +3. Next, build the workload (a.k.a buildroot Linux) with nodisk with FireMarshal. + For the rest of these steps, we will assume you are using the base ``br-base.json`` workload. This workload has basic support for GPIO and SPI drivers but you can build off it in different workloads (refer to FireMarshal docs on workload inheritance). .. code-block:: shell @@ -92,7 +92,7 @@ To make building this type of Linux binary easy, we will use the FireMarshal pla ./marshal -v -d build br-base.json # here the -d indicates --nodisk or initramfs .. Note:: Using the "board" FireMarshal functionality allows any child workload depending on ``br-base.json`` to use the "prototype" ``br-base.json`` rather than the FireChip version. - Thus you can re-use existing workloads that depend on ``br-base.json`` on the prototype platform by just changing the "board"! + Thus, you can re-use existing workloads that depend on ``br-base.json`` on the prototype platform by just changing the "board"! 4. The last step to generate the proper binary is to flatten it. This is done by using FireMarshal's install feature and will produce a ``*-flat`` binary in the ``$PATH_TO_FIREMARSHAL/images`` directory (in our case ``br-base-bin-nodisk-flat``). @@ -120,7 +120,8 @@ Additionally, these instructions assume you are using Linux with ``sudo`` privil Change the default partition alignment to `1` so you can write to sector `34`. Do this with the `l` command. -3. Create the new GPT with `o`. Click yes on all the prompts. +3. Create the new GPT with `o`. + Click yes on all the prompts. 4. Create a 512MiB partition to store the Linux binary (this can be smaller but it must be larger than the size of the Linux binary). Use `n` and select sector 34, with size `+1048576` (corresponding to 512MiB). From 9cee20ecc10105010f2cf1684aa815262da4245f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 13 Apr 2021 22:23:03 -0700 Subject: [PATCH 26/68] Address review comments --- docs/Prototyping/VCU118.rst | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 1fb4fcf9..6cfa9f32 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -47,8 +47,8 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`. -Introduction to the Bringup Platform ------------------------------------- +Introduction to the Bringup Design +---------------------------------- An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port). @@ -59,8 +59,8 @@ The TSI Host Widget is used to interact with the DUT from the prototype over a S For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables. -Running Linux with Basic and Bringup Platforms ----------------------------------------------- +Running Linux on VCU118 Designs +------------------------------- As mentioned above, the default VCU118 harness is setup with a UART and a SPI SDCard. These are utilized to both interact with the DUT (with the UART) and load in Linux (with the SDCard). @@ -69,7 +69,7 @@ The following steps describe how to build and run buildroot Linux on the prototy Building Linux with FireMarshal ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Since the prototype does not have a block device, we build Linux with the rootfs built into the binary (otherwise known as "initramfs" or "nodisk" version of Linux). +Since the prototype currently does not have a block device setup for it, we build Linux with the rootfs built into the binary (otherwise known as "initramfs" or "nodisk" version of Linux). To make building this type of Linux binary easy, we will use the FireMarshal platform (see :ref:`fire-marshal` for more information). 1. Setup FireMarshal (see :ref:`fire-marshal` on the initial setup). @@ -79,13 +79,14 @@ To make building this type of Linux binary easy, we will use the FireMarshal pla .. code-block:: shell + # this assumes you do not have a `marshal-config.yaml` file already setup echo "board-dir : 'boards/prototype'" > $PATH_TO_FIREMARSHAL/marshal-config.yaml .. Note:: Refer to the FireMarshal docs on more ways to set the board differently through environment variables and more. 3. Next, build the workload (a.k.a buildroot Linux) with nodisk with FireMarshal. For the rest of these steps, we will assume you are using the base ``br-base.json`` workload. - This workload has basic support for GPIO and SPI drivers but you can build off it in different workloads (refer to FireMarshal docs on workload inheritance). + This workload has basic support for GPIO and SPI drivers (in addition to the default UART driver) but you can build off it in different workloads (refer to FireMarshal docs on workload inheritance). .. code-block:: shell @@ -105,7 +106,7 @@ Setting up the SDCard ~~~~~~~~~~~~~~~~~~~~~ These instructions assume that you have a spare uSDCard that can be loaded with Linux and other files using two partitions. -The 1st partition will be used to store the Linux binary (created with FireMarshal or other means) while the 2nd partition will be used to store miscellaneous files. +The 1st partition will be used to store the Linux binary (created with FireMarshal or other means) while the 2nd partition will store a file system that can be accessed from the DUT. Additionally, these instructions assume you are using Linux with ``sudo`` privileges and ``gdisk`` but you can follow a similar set of steps on Mac (using ``gpt`` or another similar program). 1. Wipe the GPT on the card using ``gdisk``. From 1dd2698e112557115762b15c12444f322f2cab64 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 13 Apr 2021 22:30:35 -0700 Subject: [PATCH 27/68] Update ref in chip communication docs. --- docs/Advanced-Concepts/Chip-Communication.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 6e8d2c0e..b63a3885 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -222,4 +222,4 @@ The following image shows this flow: .. image:: ../_static/images/chip-bringup.png In fact, this exact type of bringup setup is what the following section discusses: -:ref:`Prototyping/VCU118:Introduction to the Bringup Platform`. +:ref:`Prototyping/VCU118:Introduction to the Bringup Design`. From 325f65e4dfcad7be0e9ae80e31d3140caee4563e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 14 Apr 2021 11:21:33 -0700 Subject: [PATCH 28/68] Apply suggestions from code review Co-authored-by: alonamid --- docs/Prototyping/VCU118.rst | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 6cfa9f32..9cdedc37 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -84,7 +84,7 @@ To make building this type of Linux binary easy, we will use the FireMarshal pla .. Note:: Refer to the FireMarshal docs on more ways to set the board differently through environment variables and more. -3. Next, build the workload (a.k.a buildroot Linux) with nodisk with FireMarshal. +3. Next, build the workload (a.k.a buildroot Linux) in FireMarshal with the ``nodisk`` option flag. For the rest of these steps, we will assume you are using the base ``br-base.json`` workload. This workload has basic support for GPIO and SPI drivers (in addition to the default UART driver) but you can build off it in different workloads (refer to FireMarshal docs on workload inheritance). @@ -92,7 +92,7 @@ To make building this type of Linux binary easy, we will use the FireMarshal pla ./marshal -v -d build br-base.json # here the -d indicates --nodisk or initramfs -.. Note:: Using the "board" FireMarshal functionality allows any child workload depending on ``br-base.json`` to use the "prototype" ``br-base.json`` rather than the FireChip version. +.. Note:: Using the "board" FireMarshal functionality allows any child workload depending on the ``br-base.json`` workload specification to target a "prototype" platform rather than FireChip platform. Thus, you can re-use existing workloads that depend on ``br-base.json`` on the prototype platform by just changing the "board"! 4. The last step to generate the proper binary is to flatten it. @@ -107,7 +107,7 @@ Setting up the SDCard These instructions assume that you have a spare uSDCard that can be loaded with Linux and other files using two partitions. The 1st partition will be used to store the Linux binary (created with FireMarshal or other means) while the 2nd partition will store a file system that can be accessed from the DUT. -Additionally, these instructions assume you are using Linux with ``sudo`` privileges and ``gdisk`` but you can follow a similar set of steps on Mac (using ``gpt`` or another similar program). +Additionally, these instructions assume you are using Linux with ``sudo`` privileges and ``gdisk``, but you can follow a similar set of steps on Mac (using ``gpt`` or another similar program). 1. Wipe the GPT on the card using ``gdisk``. Use the `z` command to zap everything. @@ -126,11 +126,11 @@ Additionally, these instructions assume you are using Linux with ``sudo`` privil 4. Create a 512MiB partition to store the Linux binary (this can be smaller but it must be larger than the size of the Linux binary). Use `n` and select sector 34, with size `+1048576` (corresponding to 512MiB). - For the type search for the `apfs` type and use the hex number given. + For the type, search for the `apfs` type and use the hex number given. 5. Create a second partition to store any other files with the rest of the SDCard. Use `n` and use the defaults for starting sector and overall size (expand the 2nd partition to the rest of the SDCard space). - For the type search for the `hfs` and use the hex number given. + For the type, search for the `hfs` and use the hex number given. 6. Write the changes using `w`. @@ -162,4 +162,4 @@ To interact with Linux via the UART console, you can connect to the serial port screen -S FPGA_UART_CONSOLE /dev/ttyUSB1 115200 -Once connected you should see the binary being loaded as well as Linux output (in some cases you might need to reset the DUT). +Once connected, you should see the binary being loaded as well as Linux output (in some cases you might need to reset the DUT). From 39c37563664255e7c27253adb0674e409ca420e8 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 14 Apr 2021 11:24:19 -0700 Subject: [PATCH 29/68] Update VCU118.rst --- docs/Prototyping/VCU118.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 9cdedc37..ece3ac82 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -96,7 +96,7 @@ To make building this type of Linux binary easy, we will use the FireMarshal pla Thus, you can re-use existing workloads that depend on ``br-base.json`` on the prototype platform by just changing the "board"! 4. The last step to generate the proper binary is to flatten it. - This is done by using FireMarshal's install feature and will produce a ``*-flat`` binary in the ``$PATH_TO_FIREMARSHAL/images`` directory (in our case ``br-base-bin-nodisk-flat``). + This is done by using FireMarshal's ``install`` feature which will produce a ``*-flat`` binary in the ``$PATH_TO_FIREMARSHAL/images`` directory (in our case ``br-base-bin-nodisk-flat``) from the previously built Linux binary (``br-base-bin-nodisk``). .. code-block:: shell From 87a10643660a048d13a2d8fa5f7faa62c039dfad Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 15 Apr 2021 09:36:07 -0700 Subject: [PATCH 30/68] add timing annotated targets for post-syn sim + docs update --- docs/VLSI/Advanced-Usage.rst | 28 +++++++++++++++++++++++++--- docs/VLSI/Tutorial.rst | 4 ++-- vlsi/sim.mk | 4 ++++ 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index b78eda54..2e2961f5 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -49,6 +49,28 @@ Say you need to update some power straps settings in ``example.yml`` and want to make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' -RTL and Gate-level Simulation ------------------------------ -With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. +RTL/Gate-level Simulation, Power Estimation +------------------------------------------- +With the Synopsys plugin, RTL and gate-level simulation is supported using VCS at the chip-level. Also, post-par power estimation with Voltus in the Cadence plugin is also supported. While the provided example does not implement any simulation, some Make targets are provided in the ``vlsi/`` directory. Here is a brief description: + +* ``sim-rtl``: RTL-level simulation + + * ``sim-rtl-debug``: Also write a VPD waveform + +* ``sim-syn``: Post-synthesis gate-level simulation + + * ``sim-syn-debug``: Also write a VPD waveform + * ``sim-syn-timing-debug``: Timing-annotated with VPD waveform + +* ``sim-par``: Post-par gate-level simulation + + * ``sim-par-debug``: Also write a VPD waveform + * ``sim-par-timing-debug``: Timing-annotated with VPD waveform + +* ``power-par``: Post-par power estimation + + * Note: this will run ``sim-par`` first + +* ``redo-`` can be appended to all above targets to break dependency tracking, like described above. + +The simulation configuration (e.g. binaries) can be edited for your design. See the Makefile and refer to Hammer's documentation for how to set up simulation parameters for your design. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 27e3a039..5a227d52 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -50,11 +50,11 @@ Prerequisites ------------- * Python 3.4+ -* numpy and gdspy packages +* numpy and gdspy packages. gdspy must be version 1.4. * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. + * Download the `ASAP7 PDK v1p5 `__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 6de46a90..e397e431 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -11,6 +11,8 @@ redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) redo-sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +redo-sim-syn-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug +redo-sim-syn-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) redo-sim-par: $(SIM_CONF) redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) @@ -32,6 +34,8 @@ sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +sim-syn-timing-debug: $(SIM_TIMING_CONF) sim-syn-debug +sim-syn-timing-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF) $(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-par: $(SIM_CONF) From 840eb9fdebf34664bd1bf098390151c1ada52482 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 15 Apr 2021 10:00:14 -0700 Subject: [PATCH 31/68] par -> syn typo --- vlsi/sim.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index e397e431..92225737 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -11,7 +11,7 @@ redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) redo-sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -redo-sim-syn-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug +redo-sim-syn-timing-debug: $(SIM_TIMING_CONF) redo-sim-syn-debug redo-sim-syn-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) redo-sim-par: $(SIM_CONF) From fd0ba3f315ee034455812973fa4b6212827aa8ed Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 17 Apr 2021 01:27:07 -0700 Subject: [PATCH 32/68] Synchronize JTAG reset to JTAG.TCK. --- generators/chipyard/src/main/scala/IOBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index dd74e960..501fb8df 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -231,7 +231,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ d.disableDebug.foreach { d => d := false.B } // Drive JTAG on-chip IOs d.systemjtag.map { j => - j.reset := clockBundle.reset + j.reset := ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.toBool) j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) j.version := p(JtagDTMKey).idcodeVersion.U(4.W) From c046af0de2768daa9f8a6aeb625477056f846826 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vladimir=20Milovanovi=C4=87?= Date: Sun, 18 Apr 2021 17:43:10 +0200 Subject: [PATCH 33/68] Bump tests for scalatest version change. --- .../src/test/scala/clocking/SimplePllConfigurationSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala index 0abe7c50..d80aafc1 100644 --- a/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala +++ b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala @@ -3,7 +3,7 @@ package chipyard.clocking import freechips.rocketchip.prci._ -class SimplePllConfigurationSpec extends org.scalatest.FlatSpec { +class SimplePllConfigurationSpec extends org.scalatest.flatspec.AnyFlatSpec { def genConf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration( "testPLL", From 70afebae9f17cbd6c05645623128aad6b5e39de5 Mon Sep 17 00:00:00 2001 From: Chick Markley Date: Mon, 19 Apr 2021 14:57:34 -0700 Subject: [PATCH 34/68] Runs `make clean` after `make-install` to reduce used disk (#855) * Runs `make clean` after `make-install` to reduce used disk Make install leaves many .o and other files Fixes problems with disk space on github actions runner * Create a flag --clean-after-install that can be passed as the second argument to `make_build` function. * Create a flag --clean-after-install that can be passed as the second argument to `make_build` function. Ups tools-cache-version to v7 * Now running clean after install just depends on adding an environment variable when using scripts that call `module_make` or `module_build`. Those two bash functions will check CLEANAFTERINSTALL and if it is non-empty, they will call `make clean` after other `make` calls. * build-toolchains.sh gets new flag --clean-after-install to turn enable `make clean` in `module_make` and `module_run` --- .circleci/config.yml | 2 +- scripts/build-toolchains.sh | 20 ++++++++++++-------- scripts/build-util.sh | 6 ++++++ 3 files changed, 19 insertions(+), 9 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index bdd90443..805611eb 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,7 +6,7 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v6" + default: "v7" # default execution env.s executors: diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index ec2920a2..f4d20849 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -18,11 +18,12 @@ usage() { echo " ec2fast: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" echo "" echo "Options" - echo " --prefix PREFIX : Install destination. If unset, defaults to $(pwd)/riscv-tools-install" - echo " or $(pwd)/esp-tools-install" - echo " --ignore-qemu : Ignore installing QEMU" - echo " --arch -a : Architecture (e.g., rv64gc)" - echo " --help -h : Display this message" + echo " --prefix PREFIX : Install destination. If unset, defaults to $(pwd)/riscv-tools-install" + echo " or $(pwd)/esp-tools-install" + echo " --ignore-qemu : Ignore installing QEMU" + echo " --clean-after-install : Run make clean in calls to module_make and module_build" + echo " --arch -a : Architecture (e.g., rv64gc)" + echo " --help -h : Display this message" exit "$1" } @@ -37,6 +38,7 @@ die() { TOOLCHAIN="riscv-tools" EC2FASTINSTALL="false" IGNOREQEMU="" +CLEANAFTERINSTALL="" RISCV="" ARCH="" @@ -51,9 +53,11 @@ do RISCV=$(realpath $1) ;; --ignore-qemu ) IGNOREQEMU="true" ;; - -a | --arch ) - shift - ARCH=$1 ;; + -a | --arch ) + shift + ARCH=$1 ;; + --clean-after-install ) + CLEANAFTERINSTALL="true" ;; riscv-tools | esp-tools) TOOLCHAIN=$1 ;; ec2fast ) diff --git a/scripts/build-util.sh b/scripts/build-util.sh index 892b274d..1af11aee 100644 --- a/scripts/build-util.sh +++ b/scripts/build-util.sh @@ -49,6 +49,9 @@ module_make() ( # cd "${SRCDIR}/${1}/build" shift "${MAKE}" "$@" | tee "build-${1:-make}.log" + if [ -n "$CLEANAFTERINSTALL" ] ; then + "${MAKE}" clean # get rid of intermediate files + fi ) module_build() ( # [configure-arg..] @@ -81,6 +84,9 @@ module_build() ( # [configure-arg..] "${MAKE}" echo "==> Installing ${name}" "${MAKE}" install + if [ -n "$CLEANAFTERINSTALL" ] ; then + "${MAKE}" clean # get rid of intermediate files + fi } 2>&1 | tee build.log ) From 4901e2d257bfd2762c122408b6511e8f2f8b7950 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Tue, 20 Apr 2021 02:54:29 +0000 Subject: [PATCH 35/68] remove toBool to asBool. --- generators/chipyard/src/main/scala/IOBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 501fb8df..448d4b72 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -231,7 +231,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ d.disableDebug.foreach { d => d := false.B } // Drive JTAG on-chip IOs d.systemjtag.map { j => - j.reset := ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.toBool) + j.reset := ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) j.version := p(JtagDTMKey).idcodeVersion.U(4.W) From d14513cd64ce740eb6074d5f82c9f92dcbf2a400 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 21 Apr 2021 15:29:17 -0700 Subject: [PATCH 36/68] Docker Images Comment in Docs --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index a3de22b8..180c21f6 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -16,7 +16,7 @@ In CentOS-based platforms, we recommend installing the following dependencies: .. include:: /../scripts/centos-req.sh :code: bash -In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following dependencies: +In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following dependencies. These dependancies were written based on Ubuntu 16.04 LTS and 18.04 LTS - If they don't work for you, you can try out the Docker image (:ref:`Pre-built Docker Image`) before manually installing or removing dependancies: .. include:: /../scripts/ubuntu-req.sh :code: bash From 7d32e6c0b202ddb031eec1c4d56ef37456e7876e Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Thu, 22 Apr 2021 15:27:05 -0700 Subject: [PATCH 37/68] make: Use 'fd' over 'find' if possible --- common.mk | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 00fdae8e..89e998bd 100644 --- a/common.mk +++ b/common.mk @@ -59,7 +59,12 @@ include $(base_dir)/tools/dromajo/dromajo.mk # Prerequisite lists ######################################################################################### # Returns a list of files in directory $1 with file extension $2. -lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) +# If available, use 'fd' to find the list of files, which is faster than 'find'. +ifeq ($(shell which fd),) + lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) +else + lookup_srcs = $(shell fd -L ".*\.$(2)" $(1)) +endif SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) From f08f88aac0cdf8b6396a2a65f404a7f34f027949 Mon Sep 17 00:00:00 2001 From: Karl Hallsby Date: Mon, 26 Apr 2021 12:11:47 -0500 Subject: [PATCH 38/68] Update sbt installation Bintray has gone down. SBT's website now provides these as install commands. --- scripts/centos-req.sh | 8 +++++++- scripts/ubuntu-req.sh | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index 89e8644c..c7107dbc 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -4,7 +4,13 @@ set -ex sudo yum groupinstall -y "Development tools" sudo yum install -y gmp-devel mpfr-devel libmpc-devel zlib-devel vim git java java-devel -curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm.repo + +# Install SBT https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html#Red+Hat+Enterprise+Linux+and+other+RPM-based+distributions +# sudo rm -f /etc/yum.repos.d/bintray-rpm.repo +# Use rm above if sbt installed from bintray before. +curl -L https://www.scala-sbt.org/sbt-rpm.repo > sbt-rpm.repo +sudo mv sbt-rpm.repo /etc/yum.repos.d/ + sudo yum install -y sbt texinfo gengetopt sudo yum install -y expat-devel libusb1-devel ncurses-devel cmake "perl(ExtUtils::MakeMaker)" # deps for poky diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index 3bc22c73..cb74691e 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -4,8 +4,8 @@ set -ex sudo apt-get install -y build-essential bison flex sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre -# install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html -echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list +# install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html#Ubuntu+and+other+Debian-based+distributions +echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add sudo apt-get update sudo apt-get install -y sbt From 7228a7f9b45e93b9f293d8dbac5b2f51d432422e Mon Sep 17 00:00:00 2001 From: Karl Hallsby Date: Mon, 26 Apr 2021 12:45:55 -0500 Subject: [PATCH 39/68] Add missing dependency for building verilator on Ubuntu --- scripts/ubuntu-req.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index cb74691e..cbb5230f 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -21,6 +21,7 @@ sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat c sudo apt-get install -y device-tree-compiler # install verilator +sudo apt-get install -y autoconf git clone http://git.veripool.org/git/verilator cd verilator git checkout v4.034 From 25f85ffa0e82ceb7b2aab7dc0c186e2dedcfb464 Mon Sep 17 00:00:00 2001 From: Karl Hallsby Date: Mon, 26 Apr 2021 13:50:33 -0500 Subject: [PATCH 40/68] Bump installed versions of python to 3.8 Ubuntu 20.04 LTS (the most recent LTS release) stopped shipping Python 3.6 in their default repositories. Upping it to Python 3.8 does not seem to have broken the design/elaboration process. I tested re-building Chipyard and all its dependencies using this new version, and everything appears to have remained the same. --- scripts/centos-req.sh | 4 ++-- scripts/ubuntu-req.sh | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index 89e8644c..a52aea63 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -8,11 +8,11 @@ curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm sudo yum install -y sbt texinfo gengetopt sudo yum install -y expat-devel libusb1-devel ncurses-devel cmake "perl(ExtUtils::MakeMaker)" # deps for poky -sudo yum install -y python36 patch diffstat texi2html texinfo subversion chrpath git wget +sudo yum install -y python38 patch diffstat texi2html texinfo subversion chrpath git wget # deps for qemu sudo yum install -y gtk3-devel # deps for firemarshal -sudo yum install -y python36-pip python36-devel rsync libguestfs-tools makeinfo expat ctags +sudo yum install -y python38-pip python38-devel rsync libguestfs-tools makeinfo expat ctags # Install GNU make 4.x (needed to cross-compile glibc 2.28+) sudo yum install -y centos-release-scl sudo yum install -y devtoolset-8-make diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index 3bc22c73..fc149efc 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -12,11 +12,11 @@ sudo apt-get install -y sbt sudo apt-get install -y texinfo gengetopt sudo apt-get install -y libexpat1-dev libusb-dev libncurses5-dev cmake # deps for poky -sudo apt-get install -y python3.6 patch diffstat texi2html texinfo subversion chrpath git wget +sudo apt-get install -y python3.8 patch diffstat texi2html texinfo subversion chrpath git wget # deps for qemu sudo apt-get install -y libgtk-3-dev gettext # deps for firemarshal -sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat ctags +sudo apt-get install -y python3-pip python3.8-dev rsync libguestfs-tools expat ctags # install DTC sudo apt-get install -y device-tree-compiler From 67a29f56ab3f4dbea08dcf679f7a57a34fd91555 Mon Sep 17 00:00:00 2001 From: Karl Hallsby Date: Mon, 26 Apr 2021 13:51:59 -0500 Subject: [PATCH 41/68] Use nproc to determine number of cores in CentOS verilator build --- scripts/centos-req.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index c7107dbc..1e2557b7 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -29,4 +29,4 @@ sudo yum install -y dtc git clone http://git.veripool.org/git/verilator cd verilator git checkout v4.034 -autoconf && ./configure && make -j16 && sudo make install +autoconf && ./configure && make -j$(nproc) && sudo make install From d5893adad605b9be9e9ad8a5460b5023f2b9ff25 Mon Sep 17 00:00:00 2001 From: Karl Hallsby Date: Mon, 26 Apr 2021 13:57:47 -0500 Subject: [PATCH 42/68] Install curl in Ubuntu requirements Ubuntu does not ship with curl by default any more. If we are to use curl to install SBT's required information, we must ensure it is available for use on Ubuntu. --- scripts/ubuntu-req.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index cbb5230f..ee3a9de5 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -2,6 +2,7 @@ set -ex +sudo apt-get install -y curl sudo apt-get install -y build-essential bison flex sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html#Ubuntu+and+other+Debian-based+distributions From 7f4659eb762bbdc2d2bab17bcd3f3af95448e328 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 28 Apr 2021 15:28:36 -0700 Subject: [PATCH 43/68] Fix doc breakages | Fix spelling --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 180c21f6..1194009f 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -16,7 +16,8 @@ In CentOS-based platforms, we recommend installing the following dependencies: .. include:: /../scripts/centos-req.sh :code: bash -In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following dependencies. These dependancies were written based on Ubuntu 16.04 LTS and 18.04 LTS - If they don't work for you, you can try out the Docker image (:ref:`Pre-built Docker Image`) before manually installing or removing dependancies: +In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following dependencies. +These dependencies were written based on Ubuntu 16.04 LTS and 18.04 LTS - If they don't work for you, you can try out the Docker image (:ref:`Chipyard-Basics/Initial-Repo-Setup:Pre-built Docker Image`) before manually installing or removing dependencies: .. include:: /../scripts/ubuntu-req.sh :code: bash From d5541dcffd8cccbd4d9336d93e0ad0d6567c48fa Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 3 May 2021 14:03:36 -0700 Subject: [PATCH 44/68] Bump CI image --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 805611eb..e60676a8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: ucbbar/chipyard-ci-image:ab57b7d + - image: ucbbar/chipyard-ci-image:c29770 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit From c4e2e1246d0daf9a546eae848fb2a2c5b9d4a836 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Tue, 4 May 2021 08:06:18 -0500 Subject: [PATCH 45/68] avoid git.qemu.org (#876) git.qemu.org seems to be down or under heavy load. Latest qemu seems to have changed it's .gitmodules to use gitlab. Since we're using a github.com mirror, when cloning qemu use rewrite rules to use github instead of git.qemu.org. Also install the rewrite rules recursively into the local config of qemu and it's submodules so that any further git commands done interactively by the user will also use github. Co-authored-by: Tim Snyder --- scripts/build-toolchains.sh | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index f4d20849..edc62696 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -155,7 +155,17 @@ module_all riscv-tests --prefix="${RISCV}/riscv${XLEN}-unknown-elf" --with-xlen= CC= CXX= SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv${XLEN}-unknown-elf" --host=riscv${XLEN}-unknown-elf if [ -z "$IGNOREQEMU" ] ; then -SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv${XLEN}-softmmu + echo "=> Starting qemu build" + dir="$(pwd)/toolchains/qemu" + echo "==> Initializing qemu submodule" + #since we don't want to use the global config we init passing rewrite config in to the command + git -c url.https://github.com/qemu.insteadOf=https://git.qemu.org/git submodule update --init --recursive "$dir" + echo "==> Applying url-rewriting to avoid git.qemu.org" + # and once the clones exist, we recurse through them and set the rewrite + # in the local config so that any further commands by the user have the rewrite. uggh. git, why you so ugly? + git -C "$dir" config --local url.https://github.com/qemu.insteadOf https://git.qemu.org/git + git -C "$dir" submodule foreach --recursive 'git config --local url.https://github.com/qemu.insteadOf https://git.qemu.org/git' + SRCDIR="$(pwd)/toolchains" module_build qemu --prefix="${RISCV}" --target-list=riscv${XLEN}-softmmu fi # make Dromajo From 2dc47f69b88f1be721145db0513dd6891f063411 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 4 May 2021 15:34:21 -0700 Subject: [PATCH 46/68] Re-check toolchain build --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index e60676a8..f3dbf371 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,7 +6,7 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v7" + default: "v8" # default execution env.s executors: From d9900e56c1ba89bd9e23674bfd6608b85ab0889b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Tue, 4 May 2021 19:14:45 -0500 Subject: [PATCH 47/68] test whether git.qemu.org rewrite still needed (#877) In https://github.com/ucb-bar/chipyard/pull/876#issuecomment-831639151 it was requested that we add a note to build-toolchains.sh saying that the url rewrites can be removed. I went a step further and made it self-checking. Once qemu is bumped far enough that none of it's submodules come from git.qemu.org, then the test added in this commit will fail CI during the bump PR and everyone will be reminded to remove the url renaming rules and change module_build back to module_all for qemu. Co-authored-by: Tim Snyder --- scripts/build-toolchains.sh | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index edc62696..611f50e0 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -165,6 +165,15 @@ if [ -z "$IGNOREQEMU" ] ; then # in the local config so that any further commands by the user have the rewrite. uggh. git, why you so ugly? git -C "$dir" config --local url.https://github.com/qemu.insteadOf https://git.qemu.org/git git -C "$dir" submodule foreach --recursive 'git config --local url.https://github.com/qemu.insteadOf https://git.qemu.org/git' + + # check to see whether the rewrite rules are needed any more + # If you find git.qemu.org in any .gitmodules file below qemu, you still need them + # the /dev/null redirection in the submodule grepping is to quiet non-existance of further .gitmodules + ! grep -q 'git\.qemu\.org' "$dir/.gitmodules" && \ + git -C "$dir" submodule foreach --quiet --recursive '! grep -q "git\.qemu\.org" .gitmodules 2>/dev/null' && \ + echo "==> PLEASE REMOVE qemu URL-REWRITING from scripts/build-toolchains.sh. It is no longer needed!" && exit 1 + + # now actually do the build SRCDIR="$(pwd)/toolchains" module_build qemu --prefix="${RISCV}" --target-list=riscv${XLEN}-softmmu fi From cdca36a93546f2a381b472d7519f8502579e2a8f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 5 May 2021 03:25:39 +0000 Subject: [PATCH 48/68] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index bddf17c2..0743c5a9 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bddf17c28dc43e5ed89ffa58bceda9bee64ddde6 +Subproject commit 0743c5a9410af713fb7a1c0025d6331dfedec328 From 1d52899736a01ed27b4415d5e33c9ec73a4e0568 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 00:27:11 -0700 Subject: [PATCH 49/68] Remove GenerateSimFiles and use make instead --- build.sbt | 8 +- common.mk | 8 +- .../src/main/resources/csrc/emulator.cc | 0 .../src/main/scala/ConfigFragments.scala | 3 +- .../utilities/src/main/resources/bootrom | 1 - .../utilities/src/main/scala/Simulator.scala | 143 ------------------ sims/common-sim-flags.mk | 16 ++ sims/vcs/Makefile | 16 ++ sims/verilator/Makefile | 21 ++- variables.mk | 13 +- 10 files changed, 69 insertions(+), 160 deletions(-) rename generators/{utilities => chipyard}/src/main/resources/csrc/emulator.cc (100%) delete mode 120000 generators/utilities/src/main/resources/bootrom delete mode 100644 generators/utilities/src/main/scala/Simulator.scala diff --git a/build.sbt b/build.sbt index f44eeb66..3123c4b8 100644 --- a/build.sbt +++ b/build.sbt @@ -183,7 +183,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) @@ -192,14 +192,10 @@ lazy val chipyard = (project in file("generators/chipyard")) lazy val tracegen = (project in file("generators/tracegen")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(rocketchip, sifive_cache, boom, utilities) + .dependsOn(rocketchip, sifive_cache, boom) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val utilities = (project in file("generators/utilities")) - .sourceDependency(testchipip, testchipipLib) - .settings(commonSettings) - lazy val icenet = (project in file("generators/icenet")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) diff --git a/common.mk b/common.mk index 89e998bd..b876340e 100644 --- a/common.mk +++ b/common.mk @@ -20,7 +20,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client" -EXTRA_GENERATOR_REQS ?= +EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= @@ -85,10 +85,10 @@ else endif ######################################################################################### -# create list of simulation file inputs +# copy over bootrom files ######################################################################################### -$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS) - $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name)) +$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) + cp -f $< $@ ######################################################################################### # create firrtl file rule and variables diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/chipyard/src/main/resources/csrc/emulator.cc similarity index 100% rename from generators/utilities/src/main/resources/csrc/emulator.cc rename to generators/chipyard/src/main/resources/csrc/emulator.cc diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index a36285eb..a887bc1c 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.tilelink.{HasTLBusParams} import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ +import freechips.rocketchip.stage.phases.TargetDirKey import testchipip._ import tracegen.{TraceGenSystem} @@ -36,7 +37,7 @@ import chipyard._ // ----------------------- class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")) + case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) }) // DOC include start: gpio config fragment diff --git a/generators/utilities/src/main/resources/bootrom b/generators/utilities/src/main/resources/bootrom deleted file mode 120000 index fb0b1375..00000000 --- a/generators/utilities/src/main/resources/bootrom +++ /dev/null @@ -1 +0,0 @@ -../../../../rocket-chip/bootrom \ No newline at end of file diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala deleted file mode 100644 index fa157a36..00000000 --- a/generators/utilities/src/main/scala/Simulator.scala +++ /dev/null @@ -1,143 +0,0 @@ -package utilities - -import java.io.File - -case class GenerateSimConfig( - targetDir: String = ".", - dotFName: String = "sim_files.f", - simulator: Option[Simulator] = Some(VerilatorSimulator) -) - -sealed trait Simulator -object VerilatorSimulator extends Simulator -object VCSSimulator extends Simulator - -trait HasGenerateSimConfig { - val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { - head("GenerateSimFiles", "0.1") - - opt[String]("simulator") - .abbr("sim") - .valueName("") - .action((x, c) => x match { - case "verilator" => c.copy(simulator = Some(VerilatorSimulator)) - case "vcs" => c.copy(simulator = Some(VCSSimulator)) - case "none" => c.copy(simulator = None) - case _ => throw new Exception(s"Unrecognized simulator $x") - }) - .text("Name of simulator to generate files for (verilator, vcs, none)") - - opt[String]("target-dir") - .abbr("td") - .valueName("") - .action((x, c) => c.copy(targetDir = x)) - .text("Target directory to put files") - - opt[String]("dotFName") - .abbr("df") - .valueName("") - .action((x, c) => c.copy(dotFName = x)) - .text("Name of generated dot-f file") - } -} - -object GenerateSimFiles extends App with HasGenerateSimConfig { - def addOption(file: File, cfg: GenerateSimConfig): String = { - val fname = file.getCanonicalPath - // deal with header files - if (fname.takeRight(2) == ".h") { - cfg.simulator match { - // verilator needs to explicitly include verilator.h, so use the -FI option - case Some(VerilatorSimulator) => s"-FI ${fname}" - // vcs pulls headers in with +incdir, doesn't have anything like verilator.h - case Some(VCSSimulator) => "" - case None => "" - } - } else { // do nothing otherwise - fname - } - } - def writeDotF(lines: Seq[String], cfg: GenerateSimConfig): Unit = { - writeTextToFile(lines.mkString("\n"), new File(cfg.targetDir, cfg.dotFName)) - } - // From FIRRTL - def safeFile[A](fileName: String)(code: => A) = try { code } catch { - case e@ (_: java.io.FileNotFoundException | _: NullPointerException) => throw new Exception(fileName, e) - case t: Throwable => throw t - } - // From FIRRTL - def writeResource(name: String, targetDir: String): File = { - val in = getClass.getResourceAsStream(name) - val p = java.nio.file.Paths.get(name) - val fname = p.getFileName().toString(); - - val f = new File(targetDir, fname) - val out = new java.io.FileOutputStream(f) - safeFile(name)(Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write)) - out.close() - f - } - // From FIRRTL - def writeTextToFile(text: String, file: File) { - val out = new java.io.PrintWriter(file) - out.write(text) - out.close() - } - def resources(sim: Option[Simulator]): Seq[String] = Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/testchip_tsi.cc", - "/testchipip/csrc/testchip_tsi.h", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", - "/vsrc/EICG_wrapper.v", - ) ++ (sim match { - case None => Seq() - case _ => Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", - ) - }) ++ (sim match { // simulator specific files to include - case Some(VerilatorSimulator) => Seq( - "/csrc/emulator.cc", - "/csrc/verilator.h", - ) - case Some(VCSSimulator) => Seq( - "/vsrc/TestDriver.v", - ) - case None => Seq() - }) - - def writeBootrom(): Unit = { - firrtl.FileUtils.makeDirectory("./bootrom/") - writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") - writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/") - writeResource("/bootrom/bootrom.img", "./bootrom/") - } - - def writeFiles(cfg: GenerateSimConfig): Unit = { - writeBootrom() - firrtl.FileUtils.makeDirectory(cfg.targetDir) - val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) } - writeDotF(files.map(addOption(_, cfg)), cfg) - } - - parser.parse(args, GenerateSimConfig()) match { - case Some(cfg) => writeFiles(cfg) - case _ => // error message already shown - } -} diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 766dd0d3..25af4daf 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -21,3 +21,19 @@ SIM_LDFLAGS = \ -lfesvr \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) + +SIM_FILE_REQS += \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 405cda54..a268c3ce 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -31,6 +31,22 @@ include $(base_dir)/vcs.mk default: $(sim) debug: $(sim_debug) +######################################################################################### +# simulaton requirements +######################################################################################### +SIM_FILE_REQS += \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v + +# ignore *.h files since vcs has +incdir +$(sim_files): $(SIM_FILE_REQS) + mkdir -p $(dir $(sim_files)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + ######################################################################################### # import other necessary rules and variables ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 2b250ee9..1cb3cf86 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -30,6 +30,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug WAVEFORM_FLAG=-v$(sim_out_name).vcd +include $(base_dir)/sims/common-sim-flags.mk + # If verilator seed unspecified, verilator uses srand as random seed ifdef RANDOM_SEED SEED_FLAG=+verilator+seed+I$(RANDOM_SEED) @@ -41,6 +43,23 @@ endif default: $(sim) debug: $(sim_debug) +######################################################################################### +# simulaton requirements +######################################################################################### +SIM_FILE_REQS += \ + $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h + +# add -FI for *.h files +$(sim_files): $(SIM_FILE_REQS) + mkdir -p $(dir $(sim_files)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + ######################################################################################### # import other necessary rules and variables ######################################################################################### @@ -141,8 +160,6 @@ VERILATOR_NONCC_OPTS = \ #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- -include $(base_dir)/sims/common-sim-flags.mk - VERILATOR_CXXFLAGS = \ $(SIM_CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ diff --git a/variables.mk b/variables.mk index 2843e53e..5d1e7d7f 100644 --- a/variables.mk +++ b/variables.mk @@ -106,9 +106,12 @@ endif ######################################################################################### # path to rocket-chip and testchipip ######################################################################################### -ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip -CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl +ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip +ROCKETCHIP_RSRCS_DIR = $(ROCKETCHIP_DIR)/src/main/resources +TESTCHIP_DIR = $(base_dir)/generators/testchipip +TESTCHIP_RSRCS_DIR = $(TESTCHIP_DIR)/src/main/resources +CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl +CHIPYARD_RSRCS_DIR = $(base_dir)/generators/chipyard/src/main/resources ######################################################################################### # names of various files needed to compile and run things @@ -135,7 +138,11 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img +BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) + # files that contain lists of files needed for VCS or Verilator simulation +SIM_FILE_REQS = sim_files ?= $(build_dir)/sim_files.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f From 9cdd0e1ff21c4a831c3d9bb4f0cc8b5ac27e4150 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 00:30:46 -0700 Subject: [PATCH 50/68] Replace spaces with tabs --- sims/common-sim-flags.mk | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 25af4daf..d305d392 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -32,8 +32,7 @@ SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc - + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc From 309ab68e79b9212963ee8e72e7966af043946ea2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 00:55:57 -0700 Subject: [PATCH 51/68] Use .sbtopts file --- .sbtopts | 2 ++ variables.mk | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) create mode 100644 .sbtopts diff --git a/.sbtopts b/.sbtopts new file mode 100644 index 00000000..2358d787 --- /dev/null +++ b/.sbtopts @@ -0,0 +1,2 @@ +-Dsbt.sourcemode=true +-Dsbt.workspace=$PWD/tools diff --git a/variables.mk b/variables.mk index 2843e53e..b83693e6 100644 --- a/variables.mk +++ b/variables.mk @@ -152,7 +152,10 @@ JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir= # default sbt launch command ######################################################################################### # by default build chisel3/firrtl and other subprojects from source -override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools +SBT_OPTS_FILE := $(base_dir)/.sbtopts +ifneq (,$(wildcard $(SBT_OPTS_FILE))) +override SBT_OPTS += $(subst $$PWD,$(base_dir),$(shell cat $(SBT_OPTS_FILE))) +endif SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) From f9957b2ce34d1774a9fbdcf4b165d87c55f8ac07 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 00:56:14 -0700 Subject: [PATCH 52/68] Check for BINARY flag when doing run-* --- common.mk | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 89e998bd..35352612 100644 --- a/common.mk +++ b/common.mk @@ -162,16 +162,21 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast +check-binary: +ifndef BINARY + $(error BINARY variable is not set. Set it to the simulation binary) +endif + # run normal binary with hardware-logged insn dissassembly -run-binary: $(output_dir) $(sim) +run-binary: $(output_dir) $(sim) $(check-binary) (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) # run simulator as fast as possible (no insn disassembly) -run-binary-fast: $(output_dir) $(sim) +run-binary-fast: $(output_dir) $(sim) $(check-binary) (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -182,16 +187,19 @@ run-fast: run-asm-tests-fast run-bmark-tests-fast $(binary_hex): $(output_dir) $(BINARY) $(base_dir)/scripts/smartelf2hex.sh $(BINARY) > $(binary_hex) +run-binary-hex: $(check-binary) run-binary-hex: $(output_dir) $(sim) $(binary_hex) run-binary-hex: run-binary run-binary-hex: override LOADMEM_ADDR = 80000000 run-binary-hex: override LOADMEM = $(binary_hex) run-binary-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +run-binary-debug-hex: $(check-binary) run-binary-debug-hex: $(output_dir) $(sim) $(binary_hex) run-binary-debug-hex: run-binary-debug run-binary-debug-hex: override LOADMEM_ADDR = 80000000 run-binary-debug-hex: override LOADMEM = $(binary_hex) run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +run-binary-fast-hex: $(check-binary) run-binary-fast-hex: $(output_dir) $(sim) $(binary_hex) run-binary-fast-hex: run-binary-fast run-binary-fast-hex: override LOADMEM_ADDR = 80000000 From 365e2ea81e3a24ffbf3ef32780fcdf726617fbd6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 01:11:30 -0700 Subject: [PATCH 53/68] Fix BINARY check --- common.mk | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/common.mk b/common.mk index 35352612..ac80af91 100644 --- a/common.mk +++ b/common.mk @@ -163,20 +163,20 @@ verilog: $(sim_vsrcs) .PHONY: run-binary run-binary-fast run-binary-debug run-fast check-binary: -ifndef BINARY +ifeq (,$(BINARY)) $(error BINARY variable is not set. Set it to the simulation binary) endif # run normal binary with hardware-logged insn dissassembly -run-binary: $(output_dir) $(sim) $(check-binary) +run-binary: $(output_dir) $(sim) check-binary (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) # run simulator as fast as possible (no insn disassembly) -run-binary-fast: $(output_dir) $(sim) $(check-binary) +run-binary-fast: $(output_dir) $(sim) check-binary (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -187,19 +187,19 @@ run-fast: run-asm-tests-fast run-bmark-tests-fast $(binary_hex): $(output_dir) $(BINARY) $(base_dir)/scripts/smartelf2hex.sh $(BINARY) > $(binary_hex) -run-binary-hex: $(check-binary) +run-binary-hex: check-binary run-binary-hex: $(output_dir) $(sim) $(binary_hex) run-binary-hex: run-binary run-binary-hex: override LOADMEM_ADDR = 80000000 run-binary-hex: override LOADMEM = $(binary_hex) run-binary-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -run-binary-debug-hex: $(check-binary) +run-binary-debug-hex: check-binary run-binary-debug-hex: $(output_dir) $(sim) $(binary_hex) run-binary-debug-hex: run-binary-debug run-binary-debug-hex: override LOADMEM_ADDR = 80000000 run-binary-debug-hex: override LOADMEM = $(binary_hex) run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -run-binary-fast-hex: $(check-binary) +run-binary-fast-hex: check-binary run-binary-fast-hex: $(output_dir) $(sim) $(binary_hex) run-binary-fast-hex: run-binary-fast run-binary-fast-hex: override LOADMEM_ADDR = 80000000 From 7195c0cbd1041338021c0813cd96a74940dca43b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 14:05:59 -0700 Subject: [PATCH 54/68] Check for thin client flag | Bump SBT to 1.4.9 --- common.mk | 9 +++++++-- project/build.properties | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index ac80af91..a4cb26f2 100644 --- a/common.mk +++ b/common.mk @@ -247,12 +247,17 @@ SBT_COMMAND ?= shell launch-sbt: cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)" +check-thin-client: +ifeq (,$(ENABLE_SBT_THIN_CLIENT)) + $(error ENABLE_SBT_THIN_CLIENT not set.) +endif + .PHONY: shutdown-sbt-server -shutdown-sbt-server: +shutdown-sbt-server: check-thin-client cd $(base_dir) && $(SBT) "shutdown" .PHONY: start-sbt-server -start-sbt-server: +start-sbt-server: check-thin-client cd $(base_dir) && $(SBT) "exit" ######################################################################################### diff --git a/project/build.properties b/project/build.properties index 7de0a938..dbae93bc 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.4.4 +sbt.version=1.4.9 From aa4eff3407e117deae5035d091386ba6c4273a90 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 14:08:47 -0700 Subject: [PATCH 55/68] Add small comments about thin client --- common.mk | 2 +- variables.mk | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index a4cb26f2..1278e031 100644 --- a/common.mk +++ b/common.mk @@ -18,7 +18,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ -" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client" +" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best with sbtn or sbt script)" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= diff --git a/variables.mk b/variables.mk index b83693e6..d892c8e4 100644 --- a/variables.mk +++ b/variables.mk @@ -164,6 +164,7 @@ SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading +# use with sbt script or sbtn to bypass error code issues SBT_CLIENT_FLAG = --client endif From 95f55a667f0b8f49c6dd63bc8f9b1011e01a774c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 14:45:45 -0700 Subject: [PATCH 56/68] Elaborate comments a bit more | Remove BB'ed files that are auto-copied/added --- sims/common-sim-flags.mk | 14 +------------- sims/vcs/Makefile | 2 +- sims/verilator/Makefile | 2 +- 3 files changed, 3 insertions(+), 15 deletions(-) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index d305d392..7c6c580d 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -23,16 +23,4 @@ SIM_LDFLAGS = \ $(EXTRA_SIM_LDFLAGS) SIM_FILE_REQS += \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index a268c3ce..f0fc90e5 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -37,7 +37,7 @@ debug: $(sim_debug) SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v -# ignore *.h files since vcs has +incdir +# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) $(sim_files): $(SIM_FILE_REQS) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 1cb3cf86..9c8f3fa6 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -50,7 +50,7 @@ SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h -# add -FI for *.h files +# copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) From eb85415783f25f0cf51b624b4cf1f6f8ba6a20c4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 15:09:40 -0700 Subject: [PATCH 57/68] Have Verilator build with unused simulation files --- sims/verilator/Makefile | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9c8f3fa6..00c0f1bb 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -46,9 +46,21 @@ debug: $(sim_debug) ######################################################################################### # simulaton requirements ######################################################################################### +# past emulator.cc and verilator.h, the other files may not be used in the simulation but +# are needed for emulator.cc to compile SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h + $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) From a0de9a0cfbbdc22aed9217111a7ca7b4b116067c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 20:36:28 -0700 Subject: [PATCH 58/68] Depend on build_dir --- common.mk | 3 +++ sims/vcs/Makefile | 2 +- sims/verilator/Makefile | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index b876340e..6ab88d7e 100644 --- a/common.mk +++ b/common.mk @@ -87,6 +87,9 @@ endif ######################################################################################### # copy over bootrom files ######################################################################################### +$(build_dir): + mkdir -p $@ + $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) cp -f $< $@ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index f0fc90e5..cc4d2317 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -38,7 +38,7 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 00c0f1bb..6510090e 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -63,7 +63,7 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f -$(sim_files): $(SIM_FILE_REQS) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ From 453b1b5d9506e4dc6eac73735ccb3fa2840d90a7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 22:11:02 -0700 Subject: [PATCH 59/68] Fix tutorial patch --- scripts/tutorial-patches/build.sbt.patch | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 62cecb8d..325bdfae 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,17 +1,17 @@ diff --git a/build.sbt b/build.sbt -index e80b2a5..b1989d9 100644 +index 3123c4b8..487fc428 100644 --- a/build.sbt +++ b/build.sbt @@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(libraryDependencies ++= rocketLibDeps.value) -@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) +@@ -223,11 +223,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From 2874c988024335f6325f51652809c020d2996e3f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 22:11:58 -0700 Subject: [PATCH 60/68] Add sim_files.f to fpga --- fpga/Makefile | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/fpga/Makefile b/fpga/Makefile index 1437d8bc..a7166347 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -73,6 +73,22 @@ default: $(mcs) fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND) fpga_common_script_dir := $(fpga_dir)/common/tcl +######################################################################################### +# setup misc. sim files +######################################################################################### +SIM_FILE_REQS += \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v + +# copy files but ignore *.h files in *.f (match vcs) +$(sim_files): $(SIM_FILE_REQS) | $(build_dir) + mkdir -p $(dir $(sim_files)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + ######################################################################################### # import other necessary rules and variables ######################################################################################### From 383d11c2ad1825f11f446593ba039809c70a3ccd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 22:32:40 -0700 Subject: [PATCH 61/68] Forgot to add testchip_tsi.* to verilator --- sims/verilator/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 6510090e..26cae3e4 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -52,6 +52,8 @@ SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ From 15a30a73e98bb1eb08eda92405dc3797a0bd030f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 7 May 2021 06:39:45 +0000 Subject: [PATCH 62/68] [firechip] Memomize Clock RecordMap creation to fix supernode --- .../firechip/src/main/scala/FireSim.scala | 72 +++++++++++-------- 1 file changed, 44 insertions(+), 28 deletions(-) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 95594807..79242d2e 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -37,6 +37,17 @@ object NodeIdx { } +/** + * Specifies DUT clocks for the rational clock bridge + * + * @param allClocks Seq. of RationalClocks that want a clock + * + * @param baseClockName Name of domain that the allClocks is rational to + * + * @param baseFreqRequested Freq. for the reference domain in Hz + */ +case class BuildTopClockParameters(allClocks: Seq[RationalClock], baseClockName: String, baseFreqRequested: Double) + /** * Under FireSim's current multiclock implementation there can be only a * single clock bridge. This requires, therefore, that it be instantiated in @@ -48,8 +59,9 @@ class ClockBridgeInstantiator { // Assumes that the supernode implementation results in duplicated clocks // (i.e. only 1 set of clocks is generated for all BuildTop designs) - private val _buildtopClockMap: LinkedHashMap[String, (RationalClock, Clock)] = LinkedHashMap.empty - private var _buildtopRefTuple: Option[(String, Double)] = None + private var _buildTopClockParams: Option[BuildTopClockParameters] = None + private val _buildTopClockMap: LinkedHashMap[String, (RationalClock, Clock)] = LinkedHashMap.empty + private var _buildTopClockRecord: Option[RecordMap[Clock]] = None /** * Request a clock at a particular frequency @@ -65,41 +77,43 @@ class ClockBridgeInstantiator { } /** - * Get a RecordMap of clocks for a set of input RationalClocks + * Get a RecordMap of clocks for a set of input RationalClocks. Used to drive + * the design elaborated by buildtop * - * @param allClocks Seq. of RationalClocks that want a clock - * - * @param baseClockName Name of domain that the allClocks is rational to - * - * @param baseFreqRequested Freq. for the reference domain in Hz + * @param clockMapParameters Defines the set of required clocks */ - def requestClockRecordMap(allClocks: Seq[RationalClock], baseClockName: String, baseFreqRequested: Double): RecordMap[Clock] = { - require(!_buildtopRefTuple.isDefined, "Can only request one RecordMap of Clocks") + def requestClockRecordMap(clockMapParameters: BuildTopClockParameters): RecordMap[Clock] = { + if (_buildTopClockParams.isDefined) { + require(_buildTopClockParams.get == clockMapParameters, "Must request same set of clocks on repeated invocations.") + } else { + val clockRecord = Wire(RecordMap(clockMapParameters.allClocks.map { c => (c.name, Clock()) }:_*)) + // Build up the mutable structures describing the clocks for the dut + _buildTopClockParams = Some(clockMapParameters) + _buildTopClockRecord = Some(clockRecord) - val ratClockRecordMapWire = Wire(RecordMap(allClocks.map { c => (c.name, Clock()) }:_*)) - - _buildtopRefTuple = Some((baseClockName, baseFreqRequested)) - for (clock <- allClocks) { - val clkWire = Wire(new Clock) - _buildtopClockMap(clock.name) = (clock, clkWire) - ratClockRecordMapWire(clock.name).get := clkWire + for (clock <- clockMapParameters.allClocks) { + val clockWire = Wire(new Clock) + _buildTopClockMap(clock.name) = (clock, clockWire) + clockRecord(clock.name).get := clockWire + } } - ratClockRecordMapWire + _buildTopClockRecord.get } /** * Connect all clocks requested to ClockBridge */ def instantiateFireSimClockBridge: Unit = { - require(_buildtopRefTuple.isDefined, "Must have rational clocks to assign to") - require(_buildtopClockMap.exists(_._1 == _buildtopRefTuple.get._1), - s"Provided base-clock name for rational clocks, ${_buildtopRefTuple.get._1}, doesn't match a name within specified rational clocks." + - "Available clocks:\n " + _buildtopClockMap.map(_._1).mkString("\n ")) + require(_buildTopClockParams.isDefined, "Must have rational clocks to assign to") + val BuildTopClockParameters(allClocks, refRatClockName, refRatClockFreq) = _buildTopClockParams.get + require(_buildTopClockMap.exists(_._1 == refRatClockName), + s"Provided base-clock name for rational clocks, ${refRatClockName}, doesn't match a name within specified rational clocks." + + "Available clocks:\n " + _buildTopClockMap.map(_._1).mkString("\n ")) // Simplify the RationalClocks ratio's - val refRatClock = _buildtopClockMap.find(_._1 == _buildtopRefTuple.get._1).get._2._1 - val simpleRatClocks = _buildtopClockMap.map { t => + val refRatClock = _buildTopClockMap.find(_._1 == refRatClockName).get._2._1 + val simpleRatClocks = _buildTopClockMap.map { t => val ratClock = t._2._1 ratClock.copy( multiplier = ratClock.multiplier * refRatClock.divisor, @@ -108,8 +122,7 @@ class ClockBridgeInstantiator { // Determine all the clock dividers (harness + rational clocks) // Note: Requires that the BuildTop reference frequency is requested with proper freq. - val refRatClockFreq = _buildtopRefTuple.get._2 - val refRatSinkParams = ClockSinkParameters(take=Some(ClockParameters(freqMHz=refRatClockFreq / (1000 * 1000))),name=Some(_buildtopRefTuple.get._1)) + val refRatSinkParams = ClockSinkParameters(take=Some(ClockParameters(freqMHz=refRatClockFreq / (1000 * 1000))),name=Some(refRatClockName)) val harSinkParams = _harnessClockMap.map { case (name, (freq, bundle)) => ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))),name=Some(name)) }.toSeq @@ -144,7 +157,7 @@ class ClockBridgeInstantiator { // Connect all clocks (harness + BuildTop clocks) for (clock <- allAdjRatClks) { val (_, cbClockField) = cbVecTuples.find(_._1.equalFrequency(clock)).get - _buildtopClockMap.get(clock.name).map { case (_, clk) => clk := cbClockField } + _buildTopClockMap.get(clock.name).map { case (_, clk) => clk := cbClockField } _harnessClockMap.get(clock.name).map { case (_, clk) => clk := cbClockField } } } @@ -197,7 +210,10 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => { chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset := th.buildtopReset input_clocks := p(ClockBridgeInstantiatorKey) - .requestClockRecordMap(rationalClockSpecs.toSeq, p(FireSimBaseClockNameKey), pllConfig.referenceFreqMHz * (1000 * 1000)) + .requestClockRecordMap(BuildTopClockParameters( + rationalClockSpecs.toSeq, + p(FireSimBaseClockNameKey), + pllConfig.referenceFreqMHz * (1000 * 1000))) Nil }) // return the reference frequency From 03650a20281b0c68d593a8198af4d052b76cc34e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 11 May 2021 17:27:06 -0500 Subject: [PATCH 63/68] Use root within Dockerfile --- dockerfiles/Dockerfile | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/dockerfiles/Dockerfile b/dockerfiles/Dockerfile index d9fcfa0f..61e2ea81 100644 --- a/dockerfiles/Dockerfile +++ b/dockerfiles/Dockerfile @@ -17,19 +17,7 @@ RUN apt-get update && \ keyboard-configuration \ console-setup -# Adds a new user called riscvuser -RUN groupadd --gid 3434 riscvuser \ - && useradd --uid 3434 --gid riscvuser --shell /bin/bash --create-home riscvuser \ - && echo 'riscvuser ALL=NOPASSWD: ALL' >> /etc/sudoers.d/50-riscvuser \ - && echo 'Defaults env_keep += "DEBIAN_FRONTEND"' >> /etc/sudoers.d/env_keep - -WORKDIR /home/riscvuser -USER riscvuser - -# Update PATH for RISCV toolchain (note: hardcoded for CircleCI) -ENV RISCV="/home/riscvuser/riscv-tools-install" -ENV LD_LIBRARY_PATH="$RISCV/lib" -ENV PATH="$RISCV/bin:$PATH" +WORKDIR /root # Install Chipyard and run ubuntu-req.sh to install necessary dependencies RUN git clone https://github.com/ucb-bar/chipyard.git && \ @@ -38,7 +26,6 @@ RUN git clone https://github.com/ucb-bar/chipyard.git && \ ./scripts/ubuntu-req.sh 1>/dev/null && \ sudo rm -rf /var/lib/apt/lists/* - # BUILD IMAGE WITH TOOLCHAINS # Use above build as base From 86593e294898c4b9e911e20e8ad7afe8926ac030 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 11 May 2021 17:29:07 -0500 Subject: [PATCH 64/68] Bump CI | Update entrypoint.sh for toolchain image --- .circleci/config.yml | 2 +- scripts/entrypoint.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index f3dbf371..96bddd77 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: ucbbar/chipyard-ci-image:c29770 + - image: ucbbar/chipyard-ci-image:03650a environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit diff --git a/scripts/entrypoint.sh b/scripts/entrypoint.sh index 41e5bda5..457656e8 100755 --- a/scripts/entrypoint.sh +++ b/scripts/entrypoint.sh @@ -3,6 +3,6 @@ # used with the dockerfile to set up enviroment variables by running env.sh # adapted from https://stackoverflow.com/questions/55921914/how-to-source-a-script-with-environment-variables-in-a-docker-build-process -. /home/riscvuser/chipyard/env.sh +. /root/chipyard/env.sh exec "$@" From 419a1df3e8deb8b4231a296e104e72c4930070f1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 11 May 2021 18:05:35 -0500 Subject: [PATCH 65/68] Re-bump CI image --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 96bddd77..d4415ee8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: ucbbar/chipyard-ci-image:03650a + - image: ucbbar/chipyard-ci-image:03650a2 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit From 1d51bb90db1cca25ba84b0f56256516c45814130 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 12 May 2021 18:26:01 -0500 Subject: [PATCH 66/68] Bump Dockerfile [ci skip] --- dockerfiles/Dockerfile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/dockerfiles/Dockerfile b/dockerfiles/Dockerfile index 61e2ea81..1f8ece33 100644 --- a/dockerfiles/Dockerfile +++ b/dockerfiles/Dockerfile @@ -26,6 +26,11 @@ RUN git clone https://github.com/ucb-bar/chipyard.git && \ ./scripts/ubuntu-req.sh 1>/dev/null && \ sudo rm -rf /var/lib/apt/lists/* +# Update PATH for RISCV toolchain (note: hardcoded for CircleCI) +ENV RISCV="/root/riscv-tools-install" +ENV LD_LIBRARY_PATH="$RISCV/lib" +ENV PATH="$RISCV/bin:$PATH" + # BUILD IMAGE WITH TOOLCHAINS # Use above build as base From 16cdc88c520b491035f24f8e56fef5dba07a3105 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 12 May 2021 16:42:05 -0700 Subject: [PATCH 67/68] Small comment + org. fix | Remove extra mkdirs --- fpga/Makefile | 1 - sims/vcs/Makefile | 1 - sims/verilator/Makefile | 6 +++--- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index a7166347..8b2ed28b 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -81,7 +81,6 @@ SIM_FILE_REQS += \ # copy files but ignore *.h files in *.f (match vcs) $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ $^,\ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index cc4d2317..e364830b 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -39,7 +39,6 @@ SIM_FILE_REQS += \ # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ $^,\ diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 26cae3e4..a1186acc 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -46,11 +46,12 @@ debug: $(sim_debug) ######################################################################################### # simulaton requirements ######################################################################################### -# past emulator.cc and verilator.h, the other files may not be used in the simulation but -# are needed for emulator.cc to compile SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ + +# the following files are needed for emulator.cc to compile +SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ @@ -66,7 +67,6 @@ SIM_FILE_REQS += \ # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - mkdir -p $(dir $(sim_files)) cp -f $^ $(build_dir) $(foreach file,\ $^,\ From 31fd69a3be6879318fd2415a785ccb4bfaac45d6 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 12 May 2021 23:35:08 -0500 Subject: [PATCH 68/68] Bump CI image --- .circleci/config.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index d4415ee8..fe932ecc 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,13 +6,13 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v8" + default: "v9" # default execution env.s executors: main-env: docker: - - image: ucbbar/chipyard-ci-image:03650a2 + - image: ucbbar/chipyard-ci-image:1d51bb90 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit @@ -41,7 +41,7 @@ commands: - save_cache: key: << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} paths: - - "/home/riscvuser/<< parameters.tools-version >>-install" + - "/root/<< parameters.tools-version >>-install" ssh-checkout: description: "Add SSH key and checkout code" @@ -95,7 +95,7 @@ commands: - save_cache: key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} paths: - - "/home/riscvuser/project" + - "/root/project" run-tests: description: "Run a set of tests" @@ -190,7 +190,7 @@ jobs: - save_cache: key: extra-tests-{{ .Branch }}-{{ .Revision }} paths: - - "/home/riscvuser/project/tests" + - "/root/project/tests" prepare-chipyard-cores: executor: main-env