Remove generic parameter from this PR
This commit is contained in:
@@ -25,8 +25,7 @@ import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import chipyard.{BuildTop, BuildSystem}
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import chipyard.GenericCanAttachTile
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import chipyard.{BuildTop, BuildSystem, TestSuitesKey, TestSuiteHelper}
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/**
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* TODO: Why do we need this?
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@@ -65,8 +64,11 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) =>
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class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(nL2TLBEntries = entries))).convert
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
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case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
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case other => other
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}
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})
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@@ -97,15 +99,18 @@ class WithMultiRoCC extends Config((site, here, up) => {
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*
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* @param harts harts to specify which will get a Hwacha
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*/
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class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
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case MultiRoCCKey => {
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up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
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(i -> Seq((p: Parameters) => {
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LazyModule(new Hwacha()(p)).suggestName("hwacha")
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}))
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class WithMultiRoCCHwacha(harts: Int*) extends Config(
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new chipyard.config.WithHwachaTest ++
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new Config((site, here, up) => {
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case MultiRoCCKey => {
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up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
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(i -> Seq((p: Parameters) => {
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LazyModule(new Hwacha()(p)).suggestName("hwacha")
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}))
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}
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}
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}
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})
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})
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)
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class WithTraceIO extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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@@ -120,7 +125,22 @@ class WithTraceIO extends Config((site, here, up) => {
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class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(nPerfCounters = n))).convert
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(nPerfCounters = n)))
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case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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core = tp.tileParams.core.copy(nPerfCounters = n)))
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case other => other
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}
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})
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class WithHwachaTest extends Config((site, here, up) => {
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case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
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up(TestSuitesKey).apply(tileParams, suiteHelper, p)
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import hwacha.HwachaTestSuites._
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suiteHelper.addSuites(rv64uv.map(_("p")))
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suiteHelper.addSuites(rv64uv.map(_("vp")))
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suiteHelper.addSuite(rv64sv("p"))
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suiteHelper.addSuite(hwachaBmarks)
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"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
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}
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})
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@@ -1,177 +0,0 @@
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package chipyard
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import scala.reflect.ClassTag
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import scala.reflect.runtime.universe._
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import chisel3._
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import freechips.rocketchip.config.{Parameters, Config, Field, View}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName}
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import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tile._
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// Trait for generic case class of base trait for copying
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trait ConcreteBaseTrait[Base] {
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this: Product =>
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val _origin: Base
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// Convert back to core-specific tile
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def convert: Base = {
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// Reflection Info of this class
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val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init
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// Reflection of target class
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val paramClass = _origin.getClass
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val paramNames = (paramClass.getDeclaredFields map (f => f.getName))
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val paramCtor = paramClass.getConstructors.head
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// Build a list of parameter in the original parameter class
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val nameDict = paramNames.zipWithIndex.toMap
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val indexList = fieldNames map (n => nameDict.get(n))
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val fieldList = this.productIterator.toList map {
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case c: ConcreteBaseTrait[_] => c.convert
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case v => v
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}
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val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap
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val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map
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{ case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] }
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paramCtor.newInstance(newValues:_*).asInstanceOf[Base]
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}
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}
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// Case class to change common parameters visible in the base traits. Some fields in the base traits may not be configurable as a
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// case class constructor parameter for some cores, and those field will be ignored when applied.
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case class GenericCoreParams(
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val bootFreqHz: BigInt,
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val useVM: Boolean,
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val useUser: Boolean,
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val useSupervisor: Boolean,
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val useDebug: Boolean,
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val useAtomics: Boolean,
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val useAtomicsOnlyForIO: Boolean,
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val useCompressed: Boolean,
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override val useVector: Boolean,
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val useSCIE: Boolean,
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val useRVE: Boolean,
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val mulDiv: Option[MulDivParams],
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val fpu: Option[FPUParams],
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val fetchWidth: Int,
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val decodeWidth: Int,
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val retireWidth: Int,
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val instBits: Int,
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val nLocalInterrupts: Int,
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val nPMPs: Int,
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val pmpGranularity: Int,
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val nBreakpoints: Int,
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val useBPWatch: Boolean,
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val nPerfCounters: Int,
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val haveBasicCounters: Boolean,
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val haveFSDirty: Boolean,
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val misaWritable: Boolean,
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val haveCFlush: Boolean,
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val nL2TLBEntries: Int,
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val mtvecInit: Option[BigInt],
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val mtvecWritable: Boolean,
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// The original object
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val _origin: CoreParams
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) extends CoreParams with ConcreteBaseTrait[CoreParams] {
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def this(coreParams: CoreParams) = this(
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bootFreqHz = coreParams.bootFreqHz,
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useVM = coreParams.useVM,
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useUser = coreParams.useUser,
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useSupervisor = coreParams.useSupervisor,
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useDebug = coreParams.useDebug,
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useAtomics = coreParams.useAtomics,
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useAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO,
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useCompressed = coreParams.useCompressed,
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useVector = coreParams.useVector,
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useSCIE = coreParams.useSCIE,
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useRVE = coreParams.useRVE,
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mulDiv = coreParams.mulDiv,
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fpu = coreParams.fpu,
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fetchWidth = coreParams.fetchWidth,
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decodeWidth = coreParams.decodeWidth,
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retireWidth = coreParams.retireWidth,
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instBits = coreParams.instBits,
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nLocalInterrupts = coreParams.nLocalInterrupts,
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nPMPs = coreParams.nPMPs,
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pmpGranularity = coreParams.pmpGranularity,
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nBreakpoints = coreParams.nBreakpoints,
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useBPWatch = coreParams.useBPWatch,
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nPerfCounters = coreParams.nPerfCounters,
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haveBasicCounters = coreParams.haveBasicCounters,
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haveFSDirty = coreParams.haveFSDirty,
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misaWritable = coreParams.misaWritable,
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haveCFlush = coreParams.haveCFlush,
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nL2TLBEntries = coreParams.nL2TLBEntries,
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mtvecInit = coreParams.mtvecInit,
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mtvecWritable = coreParams.mtvecWritable,
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_origin = coreParams
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)
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// Implement abstract function as placeholder
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def lrscCycles: Int = _origin.lrscCycles
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}
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case class GenericTileParams(
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val core: GenericCoreParams,
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val icache: Option[ICacheParams],
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val dcache: Option[DCacheParams],
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val btb: Option[BTBParams],
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val hartId: Int,
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val beuAddr: Option[BigInt],
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val blockerCtrlAddr: Option[BigInt],
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val name: Option[String],
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// The original object
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val _origin: TileParams,
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) extends TileParams with ConcreteBaseTrait[TileParams] {
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// Copy constructor to build the params
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def this(tileParams: TileParams) = this(
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core = new GenericCoreParams(tileParams.core),
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icache = tileParams.icache,
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dcache = tileParams.dcache,
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btb = tileParams.btb,
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hartId = tileParams.hartId,
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beuAddr = tileParams.beuAddr,
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blockerCtrlAddr = tileParams.blockerCtrlAddr,
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name = tileParams.name,
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_origin = tileParams
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)
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}
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case class GenericTileCrossingParamsLike(
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val crossingType: ClockCrossingType,
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val master: TilePortParamsLike,
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val slave: TilePortParamsLike,
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val _origin: TileCrossingParamsLike
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) extends TileCrossingParamsLike with ConcreteBaseTrait[TileCrossingParamsLike] {
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def this(crossing: TileCrossingParamsLike) = this(
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crossingType = crossing.crossingType,
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master = crossing.master,
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slave = crossing.slave,
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_origin = crossing
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)
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}
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case class GenericCanAttachTileImpl(
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val tileParams: GenericTileParams,
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val crossingParams: TileCrossingParamsLike,
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val lookup: LookupByHartIdImpl,
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val _origin: CanAttachTile,
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) extends ConcreteBaseTrait[CanAttachTile] {
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def this(param: CanAttachTile) = this(
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tileParams = new GenericTileParams(param.tileParams),
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crossingParams = new GenericTileCrossingParamsLike(param.crossingParams),
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lookup = param.lookup,
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_origin = param
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)
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}
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object GenericCanAttachTile {
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def unapply(tile: CanAttachTile) = Some(new GenericCanAttachTileImpl(tile))
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}
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@@ -107,13 +107,8 @@ class TestSuiteHelper
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/**
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* Config key of custom test suite.
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*/
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case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => Unit]((tiles, helper, p) => helper.addGenericTestSuites(tiles)(p))
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/**
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* Config fragment to add custom test suite factory function.
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*
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* @param suiteFactory Test suite factory function. It takes a list of TileParams to be instantiated and the test suite helper.
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*/
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class WithTestSuite(suiteFactory: (Seq[TileParams], TestSuiteHelper, Parameters) => Unit) extends Config((site, here, up) => {
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case TestSuitesKey => suiteFactory
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case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {
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helper.addGenericTestSuites(tiles)(p)
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// Return an empty string as makefile additional snippets
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""
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})
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@@ -106,6 +106,7 @@ class HwachaLargeBoomConfig extends Config(
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithHwachaTest ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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@@ -36,6 +36,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithHwachaTest ++
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new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
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new boom.common.WithNLargeBooms(1) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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@@ -34,6 +34,7 @@ class HwachaRocketConfig extends Config(
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new chipyard.config.WithHwachaTest ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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@@ -38,24 +38,8 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
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val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
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if (p.lift(XLen).nonEmpty)
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// If a custom test suite is set up, use the custom test suite
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if (p.lift(TestSuitesKey).nonEmpty)
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p(TestSuitesKey).apply(tileParams, suiteHelper, p)
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else
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suiteHelper.addGenericTestSuites(tileParams)
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annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
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// if hwacha parameter exists then generate its tests
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// TODO: find a more elegant way to do this. either through
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// trying to disambiguate BuildRoCC, having a AccelParamsKey,
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// or having the Accelerator/Tile add its own tests
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import hwacha.HwachaTestSuites._
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if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
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suiteHelper.addSuites(rv64uv.map(_("p")))
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suiteHelper.addSuites(rv64uv.map(_("vp")))
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suiteHelper.addSuite(rv64sv("p"))
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suiteHelper.addSuite(hwachaBmarks)
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annotations += CustomMakefragSnippet(
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"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
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}
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RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
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}
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