Remove generic parameter from this PR

This commit is contained in:
Zitao Fang
2020-06-29 11:42:34 -07:00
parent d9556e14f5
commit c85d8c4211
7 changed files with 42 additions and 217 deletions

View File

@@ -25,8 +25,7 @@ import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import chipyard.{BuildTop, BuildSystem}
import chipyard.GenericCanAttachTile
import chipyard.{BuildTop, BuildSystem, TestSuitesKey, TestSuiteHelper}
/**
* TODO: Why do we need this?
@@ -65,8 +64,11 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) =>
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries))).convert
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case other => other
}
})
@@ -97,15 +99,18 @@ class WithMultiRoCC extends Config((site, here, up) => {
*
* @param harts harts to specify which will get a Hwacha
*/
class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
case MultiRoCCKey => {
up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
(i -> Seq((p: Parameters) => {
LazyModule(new Hwacha()(p)).suggestName("hwacha")
}))
class WithMultiRoCCHwacha(harts: Int*) extends Config(
new chipyard.config.WithHwachaTest ++
new Config((site, here, up) => {
case MultiRoCCKey => {
up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
(i -> Seq((p: Parameters) => {
LazyModule(new Hwacha()(p)).suggestName("hwacha")
}))
}
}
}
})
})
)
class WithTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -120,7 +125,22 @@ class WithTraceIO extends Config((site, here, up) => {
class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case GenericCanAttachTile(tp) => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n))).convert
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case other => other
}
})
class WithHwachaTest extends Config((site, here, up) => {
case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
up(TestSuitesKey).apply(tileParams, suiteHelper, p)
import hwacha.HwachaTestSuites._
suiteHelper.addSuites(rv64uv.map(_("p")))
suiteHelper.addSuites(rv64uv.map(_("vp")))
suiteHelper.addSuite(rv64sv("p"))
suiteHelper.addSuite(hwachaBmarks)
"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
}
})

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@@ -1,177 +0,0 @@
package chipyard
import scala.reflect.ClassTag
import scala.reflect.runtime.universe._
import chisel3._
import freechips.rocketchip.config.{Parameters, Config, Field, View}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName}
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
// Trait for generic case class of base trait for copying
trait ConcreteBaseTrait[Base] {
this: Product =>
val _origin: Base
// Convert back to core-specific tile
def convert: Base = {
// Reflection Info of this class
val fieldNames = (this.getClass.getDeclaredFields map (f => f.getName)).init
// Reflection of target class
val paramClass = _origin.getClass
val paramNames = (paramClass.getDeclaredFields map (f => f.getName))
val paramCtor = paramClass.getConstructors.head
// Build a list of parameter in the original parameter class
val nameDict = paramNames.zipWithIndex.toMap
val indexList = fieldNames map (n => nameDict.get(n))
val fieldList = this.productIterator.toList map {
case c: ConcreteBaseTrait[_] => c.convert
case v => v
}
val fieldDict = ((indexList zip fieldList) collect { case (Some(i), v) => (i, v) }).toMap
val newValues = _origin.asInstanceOf[Product].productIterator.toList.zipWithIndex map
{ case (v, i) => (if (fieldDict contains i) fieldDict(i) else v).asInstanceOf[AnyRef] }
paramCtor.newInstance(newValues:_*).asInstanceOf[Base]
}
}
// Case class to change common parameters visible in the base traits. Some fields in the base traits may not be configurable as a
// case class constructor parameter for some cores, and those field will be ignored when applied.
case class GenericCoreParams(
val bootFreqHz: BigInt,
val useVM: Boolean,
val useUser: Boolean,
val useSupervisor: Boolean,
val useDebug: Boolean,
val useAtomics: Boolean,
val useAtomicsOnlyForIO: Boolean,
val useCompressed: Boolean,
override val useVector: Boolean,
val useSCIE: Boolean,
val useRVE: Boolean,
val mulDiv: Option[MulDivParams],
val fpu: Option[FPUParams],
val fetchWidth: Int,
val decodeWidth: Int,
val retireWidth: Int,
val instBits: Int,
val nLocalInterrupts: Int,
val nPMPs: Int,
val pmpGranularity: Int,
val nBreakpoints: Int,
val useBPWatch: Boolean,
val nPerfCounters: Int,
val haveBasicCounters: Boolean,
val haveFSDirty: Boolean,
val misaWritable: Boolean,
val haveCFlush: Boolean,
val nL2TLBEntries: Int,
val mtvecInit: Option[BigInt],
val mtvecWritable: Boolean,
// The original object
val _origin: CoreParams
) extends CoreParams with ConcreteBaseTrait[CoreParams] {
def this(coreParams: CoreParams) = this(
bootFreqHz = coreParams.bootFreqHz,
useVM = coreParams.useVM,
useUser = coreParams.useUser,
useSupervisor = coreParams.useSupervisor,
useDebug = coreParams.useDebug,
useAtomics = coreParams.useAtomics,
useAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO,
useCompressed = coreParams.useCompressed,
useVector = coreParams.useVector,
useSCIE = coreParams.useSCIE,
useRVE = coreParams.useRVE,
mulDiv = coreParams.mulDiv,
fpu = coreParams.fpu,
fetchWidth = coreParams.fetchWidth,
decodeWidth = coreParams.decodeWidth,
retireWidth = coreParams.retireWidth,
instBits = coreParams.instBits,
nLocalInterrupts = coreParams.nLocalInterrupts,
nPMPs = coreParams.nPMPs,
pmpGranularity = coreParams.pmpGranularity,
nBreakpoints = coreParams.nBreakpoints,
useBPWatch = coreParams.useBPWatch,
nPerfCounters = coreParams.nPerfCounters,
haveBasicCounters = coreParams.haveBasicCounters,
haveFSDirty = coreParams.haveFSDirty,
misaWritable = coreParams.misaWritable,
haveCFlush = coreParams.haveCFlush,
nL2TLBEntries = coreParams.nL2TLBEntries,
mtvecInit = coreParams.mtvecInit,
mtvecWritable = coreParams.mtvecWritable,
_origin = coreParams
)
// Implement abstract function as placeholder
def lrscCycles: Int = _origin.lrscCycles
}
case class GenericTileParams(
val core: GenericCoreParams,
val icache: Option[ICacheParams],
val dcache: Option[DCacheParams],
val btb: Option[BTBParams],
val hartId: Int,
val beuAddr: Option[BigInt],
val blockerCtrlAddr: Option[BigInt],
val name: Option[String],
// The original object
val _origin: TileParams,
) extends TileParams with ConcreteBaseTrait[TileParams] {
// Copy constructor to build the params
def this(tileParams: TileParams) = this(
core = new GenericCoreParams(tileParams.core),
icache = tileParams.icache,
dcache = tileParams.dcache,
btb = tileParams.btb,
hartId = tileParams.hartId,
beuAddr = tileParams.beuAddr,
blockerCtrlAddr = tileParams.blockerCtrlAddr,
name = tileParams.name,
_origin = tileParams
)
}
case class GenericTileCrossingParamsLike(
val crossingType: ClockCrossingType,
val master: TilePortParamsLike,
val slave: TilePortParamsLike,
val _origin: TileCrossingParamsLike
) extends TileCrossingParamsLike with ConcreteBaseTrait[TileCrossingParamsLike] {
def this(crossing: TileCrossingParamsLike) = this(
crossingType = crossing.crossingType,
master = crossing.master,
slave = crossing.slave,
_origin = crossing
)
}
case class GenericCanAttachTileImpl(
val tileParams: GenericTileParams,
val crossingParams: TileCrossingParamsLike,
val lookup: LookupByHartIdImpl,
val _origin: CanAttachTile,
) extends ConcreteBaseTrait[CanAttachTile] {
def this(param: CanAttachTile) = this(
tileParams = new GenericTileParams(param.tileParams),
crossingParams = new GenericTileCrossingParamsLike(param.crossingParams),
lookup = param.lookup,
_origin = param
)
}
object GenericCanAttachTile {
def unapply(tile: CanAttachTile) = Some(new GenericCanAttachTileImpl(tile))
}

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@@ -107,13 +107,8 @@ class TestSuiteHelper
/**
* Config key of custom test suite.
*/
case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => Unit]((tiles, helper, p) => helper.addGenericTestSuites(tiles)(p))
/**
* Config fragment to add custom test suite factory function.
*
* @param suiteFactory Test suite factory function. It takes a list of TileParams to be instantiated and the test suite helper.
*/
class WithTestSuite(suiteFactory: (Seq[TileParams], TestSuiteHelper, Parameters) => Unit) extends Config((site, here, up) => {
case TestSuitesKey => suiteFactory
case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {
helper.addGenericTestSuites(tiles)(p)
// Return an empty string as makefile additional snippets
""
})

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@@ -106,6 +106,7 @@ class HwachaLargeBoomConfig extends Config(
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++

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@@ -36,6 +36,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
new boom.common.WithNLargeBooms(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++

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@@ -34,6 +34,7 @@ class HwachaRocketConfig extends Config(
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++

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@@ -38,24 +38,8 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
if (p.lift(XLen).nonEmpty)
// If a custom test suite is set up, use the custom test suite
if (p.lift(TestSuitesKey).nonEmpty)
p(TestSuitesKey).apply(tileParams, suiteHelper, p)
else
suiteHelper.addGenericTestSuites(tileParams)
annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
// if hwacha parameter exists then generate its tests
// TODO: find a more elegant way to do this. either through
// trying to disambiguate BuildRoCC, having a AccelParamsKey,
// or having the Accelerator/Tile add its own tests
import hwacha.HwachaTestSuites._
if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
suiteHelper.addSuites(rv64uv.map(_("p")))
suiteHelper.addSuites(rv64uv.map(_("vp")))
suiteHelper.addSuite(rv64sv("p"))
suiteHelper.addSuite(hwachaBmarks)
annotations += CustomMakefragSnippet(
"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
}
RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
}