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Bore out a bus clock to drive DebugIO from ChipTop

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This commit is contained in:
Jerry Zhao
2020-08-30 18:10:52 -07:00
parent 17239c56f8
commit c8448cc3e1
1 changed files with 13 additions and 3 deletions
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16
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -2,6 +2,7 @@ package chipyard
package object iobinders { package object iobinders {
import chisel3._ import chisel3._
import chisel3.util.experimental.{BoringUtils}
import chisel3.experimental.{Analog, IO} import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.config.{Field, Config, Parameters}
@@ -171,12 +172,19 @@ object AddIOCells {
*/ */
def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = { def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = {
system.debug.map { debug => system.debug.map { debug =>
val tlbus = system.outer.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
val debug_clock = Wire(Clock()).suggestName("debug_clock")
val debug_reset = Wire(Reset()).suggestName("debug_reset")
debug_clock := false.B.asClock
debug_reset := false.B
BoringUtils.bore(tlbus.module.clock, Seq(debug_clock))
BoringUtils.bore(tlbus.module.reset, Seq(debug_reset))
// We never use the PSDIO, so tie it off on-chip // We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
// Set resetCtrlOpt with the system reset // Set resetCtrlOpt with the system reset
system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := system.reset.asBool } } system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := debug_reset.asBool } }
system.debug.map { d => system.debug.map { d =>
// Tie off extTrigger // Tie off extTrigger
@@ -190,7 +198,7 @@ object AddIOCells {
// Drive JTAG on-chip IOs // Drive JTAG on-chip IOs
d.systemjtag.map { j => d.systemjtag.map { j =>
j.reset := system.reset j.reset := debug_reset
j.mfr_id := system.p(JtagDTMKey).idcodeManufId.U(11.W) j.mfr_id := system.p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := system.p(JtagDTMKey).idcodePartNum.U(16.W) j.part_number := system.p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W) j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W)
@@ -199,7 +207,9 @@ object AddIOCells {
// Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to // Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to
Debug.connectDebugClockAndReset(Some(debug), system.clock)(system.p)
Debug.connectDebugClockAndReset(Some(debug), debug_clock)(system.p)
// Add IOCells for the DMI/JTAG/APB ports // Add IOCells for the DMI/JTAG/APB ports