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vlsi/example-designs/sky130-commercial.yml

@@ -9,7 +9,7 @@ vlsi.inputs.clocks: [
 # If overriding the placement constraints in example-sky130.yml,
 # ensure one of the toplevel margin sides corresponding with the power pin metal layers
 # is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
-# For example, in example-sky130.yml we set 
+# For example, in example-sky130.yml we set
 #   par.generate_power_straps_options.by_tracks.pin_layers: 'met5'  # horizontal layer
 # therefore we must also set:
 #   vlsi.inputs.placement_constraints:

vlsi/example-designs/sky130-openroad-rockettile.yml

@@ -44,7 +44,7 @@ vlsi.inputs.placement_constraints:
     x: 50
     y: 1250
     orientation: r90
- 
+
   # tag array
   - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
     type: hardmacro

vlsi/example-designs/sky130-openroad.yml

@@ -28,7 +28,7 @@ par.openroad:
   clock_tree_resize.setup_margin: 0.0
   clock_tree_resize.hold_margin: 0.20
   global_route_resize.hold_margin: 0.60
-  clock_tree_resize.hold_max_buffer_percent: 80  
+  clock_tree_resize.hold_max_buffer_percent: 80
 
   global_placement.routing_adjustment: 0.5
   global_route.routing_adjustment: 0.3
@@ -76,7 +76,7 @@ vlsi.inputs.placement_constraints:
     x: 50
     y: 1250
     orientation: r90
- 
+
   # tag array
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
     type: hardmacro