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abejgonzalez
2023-08-28 14:56:55 -07:00
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docs/Simulation/Software-RTL-Simulation.rst
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@@ -187,7 +187,7 @@ During verilog creation, a graphml file is emitted that will allow you to visual
To view the graph, first download a viewer such as `yEd <https://www.yworks.com/products/yed/>`__.
The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer.
The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer.
To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings.
.. _sw-sim-verilator-opts: