From c7ea3b6a47cbcb2a6eff55e04cb1005aa82b6770 Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Wed, 8 Mar 2023 13:01:42 -0800 Subject: [PATCH] Minor clarification in visualization section --- docs/Simulation/Software-RTL-Simulation.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index dbd5d92c..d62f6f1c 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -191,11 +191,11 @@ If you have Synopsys licenses, we recommend using the DVE waveform viewer. Visualizing Chipyard SoCs -------------------------- -During the creation of the simulation executable, a graphml file is emitted that will allow you to visualize your Chipyard SoC in a graph format. +During verilog creation, a graphml file is emitted that will allow you to visualize your Chipyard SoC as a diplomacy graph. To view the graph, first download a viewer such as `yEd `__. -The ``*.graphml`` file will be located in ``generated-src/<...>--/``. Open the file in the graph viewer. +The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer. To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings. .. _sw-sim-verilator-opts: