Port to MDF library and start re-developing tests
This commit is contained in:
Edward Wang
@@ -6,133 +6,70 @@ import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import firrtl.Utils.{ceilLog2, BoolType}
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import scala.util.parsing.json.JSON // Todo: this will be gone
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import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
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import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge}
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import java.io.File
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import scala.language.implicitConversions
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trait PortPolarity
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case object ActiveLow extends PortPolarity
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case object ActiveHigh extends PortPolarity
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case object NegativeEdge extends PortPolarity
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case object PositiveEdge extends PortPolarity
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object PortPolarity {
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implicit def toPortPolarity(s: Any): PortPolarity =
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s match {
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case "active low" => ActiveLow
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case "active high" => ActiveHigh
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case "negative edge" => NegativeEdge
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case "positive edge" => PositiveEdge
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case _ => throw new firrtl.passes.PassException(s"Wrong port polarity: ${s.toString}")
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}
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implicit def toPortPolarity(s: Option[Any]): Option[PortPolarity] =
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s map toPortPolarity
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}
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class FirrtlMacroPort(port: MacroPort) {
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val src = port
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case class MacroPort(
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clockName: String,
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clockPolarity: Option[PortPolarity],
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addressName: String,
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addressPolarity: Option[PortPolarity],
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inputName: Option[String],
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inputPolarity: Option[PortPolarity],
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outputName: Option[String],
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outputPolarity: Option[PortPolarity],
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chipEnableName: Option[String],
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chipEnablePolarity: Option[PortPolarity],
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readEnableName: Option[String],
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readEnablePolarity: Option[PortPolarity],
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writeEnableName: Option[String],
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writeEnablePolarity: Option[PortPolarity],
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maskName: Option[String],
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maskPolarity: Option[PortPolarity],
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maskGran: Option[BigInt],
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width: BigInt,
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depth: BigInt) {
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val effectiveMaskGran = maskGran.getOrElse(width)
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val addrType = UIntType(IntWidth(ceilLog2(depth) max 1))
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val dataType = UIntType(IntWidth(width))
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val maskType = UIntType(IntWidth(width / effectiveMaskGran))
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val isReader = !port.readEnable.isEmpty && port.writeEnable.isEmpty
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val isWriter = !port.writeEnable.isEmpty && port.readEnable.isEmpty
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val isReadWriter = !port.writeEnable.isEmpty && !port.readEnable.isEmpty
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val AddrType = UIntType(IntWidth(ceilLog2(port.depth) max 1))
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val DataType = UIntType(IntWidth(port.width))
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val MaskType = UIntType(IntWidth(port.width / port.effectiveMaskGran))
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// Bundle representing this macro port.
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val tpe = BundleType(Seq(
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Field(clockName, Flip, ClockType),
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Field(addressName, Flip, addrType)) ++
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(inputName map (Field(_, Flip, dataType))) ++
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(outputName map (Field(_, Default, dataType))) ++
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(chipEnableName map (Field(_, Flip, BoolType))) ++
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(readEnableName map (Field(_, Flip, BoolType))) ++
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(writeEnableName map (Field(_, Flip, BoolType))) ++
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(maskName map (Field(_, Flip, maskType)))
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Field(port.clock.name, Flip, ClockType),
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Field(port.address.name, Flip, AddrType)) ++
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(port.input map (p => Field(p.name, Flip, DataType))) ++
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(port.output map (p => Field(p.name, Default, DataType))) ++
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(port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++
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(port.readEnable map (p => Field(p.name, Flip, BoolType))) ++
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(port.writeEnable map (p => Field(p.name, Flip, BoolType))) ++
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(port.maskPort map (p => Field(p.name, Flip, MaskType)))
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)
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val ports = tpe.fields map (f => Port(
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NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))
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}
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class Macro(lib: Map[String, Any]) {
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val name = lib("name").asInstanceOf[String]
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val width = BigInt(lib("width").asInstanceOf[Double].toLong)
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val depth = BigInt(lib("depth").asInstanceOf[Double].toLong)
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val ports = lib("ports").asInstanceOf[List[_]] map { x =>
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val map = x.asInstanceOf[Map[String, Any]]
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MacroPort(
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map("clock port name").asInstanceOf[String],
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map get "clock port polarity",
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map("address port name").asInstanceOf[String],
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map get "address port polarity",
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map get "input port name" map (_.asInstanceOf[String]),
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map get "input port polarity",
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map get "output port name" map (_.asInstanceOf[String]),
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map get "output port polarity",
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map get "chip enable port name" map (_.asInstanceOf[String]),
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map get "chip enable port polarity",
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map get "read enable port name" map (_.asInstanceOf[String]),
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map get "read enable port polarity",
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map get "write enable port name" map (_.asInstanceOf[String]),
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map get "write enable port polarity",
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map get "mask port name" map (_.asInstanceOf[String]),
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map get "mask port polarity",
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map get "mask granularity" map (x => BigInt(x.asInstanceOf[Double].toLong)),
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width,
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depth
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)
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}
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val writers = ports filter (p => p.inputName.isDefined && !p.outputName.isDefined)
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val readers = ports filter (p => !p.inputName.isDefined && p.outputName.isDefined)
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val readwriters = ports filter (p => p.inputName.isDefined && p.outputName.isDefined)
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// Reads an SRAMMacro and generates firrtl blackboxes.
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class Macro(srcMacro: SRAMMacro) {
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val src = srcMacro
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val firrtlPorts = srcMacro.ports map { new FirrtlMacroPort(_) }
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val writers = firrtlPorts filter (p => p.isReader)
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val readers = firrtlPorts filter (p => p.isWriter)
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val readwriters = firrtlPorts filter (p => p.isReadWriter)
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val sortedPorts = writers ++ readers ++ readwriters
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val extraPorts = lib get "extra ports" match {
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case None => Nil
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case Some(p) => p.asInstanceOf[List[_]] map { x =>
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val map = x.asInstanceOf[Map[String, Any]]
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assert(map("type").asInstanceOf[String] == "constant") // TODO: release it?
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val name = map("name").asInstanceOf[String]
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val width = BigInt(map("width").asInstanceOf[Double].toLong)
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val value = BigInt(map("value").asInstanceOf[Double].toLong)
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(name -> UIntLiteral(value, IntWidth(width)))
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}
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val extraPorts = srcMacro.extraPorts map { p =>
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assert(p.portType == Constant) // TODO: release it?
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val name = p.name
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val width = BigInt(p.width.asInstanceOf[Double].toLong)
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val value = BigInt(p.value.asInstanceOf[Double].toLong)
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(name -> UIntLiteral(value, IntWidth(width)))
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}
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val tpe = BundleType(ports flatMap (_.tpe.fields))
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private val modPorts = (ports flatMap (_.ports)) ++
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// Bundle representing this memory blackbox
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val tpe = BundleType(firrtlPorts flatMap (_.tpe.fields))
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private val modPorts = (firrtlPorts flatMap (_.ports)) ++
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(extraPorts map { case (name, value) => Port(NoInfo, name, Input, value.tpe) })
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val blackbox = ExtModule(NoInfo, name, modPorts, name, Nil)
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def module(body: Statement) = Module(NoInfo, name, modPorts, body)
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val blackbox = ExtModule(NoInfo, srcMacro.name, modPorts, srcMacro.name, Nil)
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def module(body: Statement) = Module(NoInfo, srcMacro.name, modPorts, body)
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}
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object Utils {
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def readJSON(file: Option[File]): Option[Seq[Map[String, Any]]] = file match {
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case None => None
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case Some(f) => try {
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(JSON parseFull io.Source.fromFile(f).mkString) match {
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case Some(p: List[Any]) => Some(
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(p foldLeft Seq[Map[String, Any]]()){
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case (res, x: Map[_, _]) =>
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val map = x.asInstanceOf[Map[String, Any]]
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if (map("type").asInstanceOf[String] == "sram") res :+ map else res
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case (res, _) => res
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}
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)
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case _ => Some(Nil)
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}
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} catch {
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case _: Throwable => Some(Nil)
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def filterForSRAM(s: Option[Seq[mdf.macrolib.Macro]]): Option[Seq[mdf.macrolib.SRAMMacro]] = {
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s match {
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case Some(l:Seq[mdf.macrolib.Macro]) => Some(l filter { _.macroType == mdf.macrolib.SRAM } map { m => m.asInstanceOf[mdf.macrolib.SRAMMacro] })
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case _ => None
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}
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}
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@@ -147,7 +84,11 @@ object Utils {
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def not(e: Expression) =
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DoPrim(PrimOps.Not, Seq(e), Nil, e.tpe)
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def invert(exp: Expression, polarity: Option[PortPolarity]) =
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// Convert a port to a FIRRTL expression, handling polarity along the way.
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def portToExpression(pp: PolarizedPort): Expression =
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portToExpression(WRef(pp.name), Some(pp.polarity))
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def portToExpression(exp: Expression, polarity: Option[PortPolarity]): Expression =
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polarity match {
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case Some(ActiveLow) | Some(NegativeEdge) => not(exp)
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case _ => exp
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