Point to SiFive license | Add require on Arty

fpga/src/main/resources/vcu118/sdboot/common.h

@@ -1,3 +1,4 @@
+// See LICENSE.Sifive for license details.
 #ifndef _SDBOOT_COMMON_H
 #define _SDBOOT_COMMON_H
 

fpga/src/main/resources/vcu118/sdboot/head.S

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #include <platform.h>
 #include <smp.h>
 #include "common.h"

fpga/src/main/resources/vcu118/sdboot/include/bits.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #ifndef _RISCV_BITS_H
 #define _RISCV_BITS_H
 

fpga/src/main/resources/vcu118/sdboot/include/const.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 /* Derived from <linux/const.h> */
 
 #ifndef _SIFIVE_CONST_H

fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 
 #ifndef _SIFIVE_CLINT_H
 #define _SIFIVE_CLINT_H
@@ -11,4 +11,4 @@
 #define CLINT_MTIME 0xBFF8
 #define CLINT_MTIME_size 0x8
 
-#endif /* _SIFIVE_CLINT_H */ 
+#endif /* _SIFIVE_CLINT_H */

fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 
 #ifndef _SIFIVE_GPIO_H
 #define _SIFIVE_GPIO_H

fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 
 #ifndef PLIC_H
 #define PLIC_H

fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 
 #ifndef _SIFIVE_SPI_H
 #define _SIFIVE_SPI_H

fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 
 #ifndef _SIFIVE_UART_H
 #define _SIFIVE_UART_H

fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #ifndef _RISCV_TEST_DEFAULTS_H
 #define _RISCV_TEST_DEFAULTS_H
 

fpga/src/main/resources/vcu118/sdboot/include/sections.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #ifndef _SECTIONS_H
 #define _SECTIONS_H
 

fpga/src/main/resources/vcu118/sdboot/include/smp.h

@@ -1,3 +1,4 @@
+// See LICENSE.Sifive for license details.
 #ifndef SIFIVE_SMP
 #define SIFIVE_SMP
 #include "platform.h"
@@ -14,7 +15,7 @@
 #define NONSMP_HART 0
 #endif
 
-/* If your test cannot handle multiple-threads, use this: 
+/* If your test cannot handle multiple-threads, use this:
  *   smp_disable(reg1)
  */
 #define smp_disable(reg1, reg2)			 \

fpga/src/main/resources/vcu118/sdboot/kprintf.c

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #include <stdarg.h>
 #include <stdint.h>
 #include <stdbool.h>

fpga/src/main/resources/vcu118/sdboot/kprintf.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #ifndef _SDBOOT_KPRINTF_H
 #define _SDBOOT_KPRINTF_H
 

fpga/src/main/resources/vcu118/sdboot/sd.c

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+// See LICENSE.Sifive for license details.
 #include <stdint.h>
 
 #include <platform.h>

fpga/src/main/scala/arty/HarnessBinders.scala

@@ -16,6 +16,8 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
 
 class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
   (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
+    require(ports.size == 2)
+
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       // Debug module reset
       th.dut_ndreset := ports(0)