diff --git a/vlsi/Makefile b/vlsi/Makefile
index e969ba14..a9e3d3a5 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -31,10 +31,8 @@ MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\
 ENV_YML            ?= $(vlsi_dir)/env.yml
 INPUT_CONFS        ?= $(if $(filter $(tech_name),nangate45),\
                         example-nangate45.yml,\
-                        example.yml)
-HAMMER_EXEC        ?= $(if $(filter $(tech_name),nangate45),\
-                        example-vlsi-nangate45,\
-                        example-vlsi)
+                        example-asap7.yml)
+HAMMER_EXEC        ?= example-vlsi
 VLSI_TOP           ?= $(TOP)
 VLSI_HARNESS_DUT_NAME ?= dut
 VLSI_OBJ_DIR       ?= $(vlsi_dir)/build
diff --git a/vlsi/example.yml b/vlsi/example-asap7.yml
similarity index 100%
rename from vlsi/example.yml
rename to vlsi/example-asap7.yml
diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml
index b4c1288a..7d43d068 100644
--- a/vlsi/example-nangate45.yml
+++ b/vlsi/example-nangate45.yml
@@ -1,15 +1,22 @@
+#----------------------
 # Technology Setup
+#----------------------
+
 vlsi.core.technology: nangate45
 
-# Specify dir with ASAP7 tarball
+# the nangate45.tech.json can't reference the $OPENROAD environment variable,
+# so we need to set the install dir here. 
 # TODO: figure out how to remove this, or override it within OpenROADTool
 technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD"
 
 vlsi.core.max_threads: 12
 
+#----------------------
 # General Hammer Inputs
+#----------------------
 
-# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
+# Hammer will auto-generate a CPF for simple power designs; 
+# see hammer/src/hammer-vlsi/defaults.yml for more info
 vlsi.inputs.power_spec_mode: "auto"
 vlsi.inputs.power_spec_type: "cpf"
 
@@ -21,125 +28,45 @@ vlsi.inputs.clocks: [
 # Generate Make include to aid in flow 
 vlsi.core.build_system: make
 
-# Power Straps
-#par.power_straps_mode: generate
-#par.generate_power_straps_method: by_tracks
-#par.blockage_spacing: 2.0
-#par.generate_power_straps_options:
-#  by_tracks:
-#    strap_layers:
-#      - metal3
-#      - metal4
-#      - metal5
-#      - metal6
-#      - metal7
-#      - metal8
-#    pin_layers:
-#      - metal7
-#      - metal8
-#    track_width: 7 # minimum allowed for M2 & M3
-#    track_spacing: 0
-#    track_spacing_M3: 1 # to avoid M2 shorts at higher density
-#    track_start: 10
-#    power_utilization: 0.05
-#    power_utilization_M8: 1.0
-#    power_utilization_M9: 1.0
-
+#----------------------
 # Placement Constraints
-# For ASAP7, all numbers must be 4x larger than final GDS
+#----------------------
+
+# For nangate45, size should be multiple of (0.19,1.4) placement grid
 vlsi.inputs.placement_constraints:
   - path: "ChipTop"
     type: toplevel
     x: 0
     y: 0
-    width: 1387.38 
-    height: 1199.1
+    width: 3334.72
+    height: 2398.2
     margins: 
       left: 0
       right: 0
       top: 0
       bottom: 0
-#  - path: "Sha3AccelwBB/dco"
-#    type: hardmacro
-#    x: 108
-#    y: 108
-#    width: 128
-#    height: 128
-#    orientation: r0
-#    top_layer: M9
-#  - path: "Sha3AccelwBB/place_obs_bottom"
-#    type: obstruction
-#    obs_types: ["place"]
-#    x: 0
-#    y: 0
-#    width: 300
-#    height: 1.08 # 1 core site tall, necessary to avoid shorts
-
-# Pin placement constraints
-#vlsi.inputs.pin_mode: generated
-#vlsi.inputs.pin.generate_mode: semi_auto
-#vlsi.inputs.pin.assignments: [
-#  {pins: "*", layers: ["metal7", "metal8"]}
-#]
-
-# Paths to extra libraries
-#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
-#vlsi.technology.extra_libraries:
-#  - library:
-#      nldm liberty file_deepsubst_meta: "local"
-#      nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
-#      lef file_deepsubst_meta: "local"
-#      lef file: "extra_libraries/example/ExampleDCO.lef"
-#      gds file_deepsubst_meta: "local"
-#      gds file: "extra_libraries/example/ExampleDCO.gds"
-#      corner:
-#        nmos: "slow"
-#        pmos: "slow"
-#        temperature: "100 C"
-#      supplies:
-#        VDD: "0.63 V"
-#        GND: "0 V"
-#  - library:
-#      nldm liberty file_deepsubst_meta: "local"
-#      nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
-#      lef file_deepsubst_meta: "local"
-#      lef file: "extra_libraries/example/ExampleDCO.lef"
-#      gds file_deepsubst_meta: "local"
-#      gds file: "extra_libraries/example/ExampleDCO.gds"
-#      corner:
-#        nmos: "fast"
-#        pmos: "fast"
-#        temperature: "0 C"
-#      supplies:
-#        VDD: "0.77 V"
-#        GND: "0 V"
-
-# Because the DCO is a dummy layout, we treat it as a physical-only cell
-#par.inputs.physical_only_cells_mode: append
-#par.inputs.physical_only_cells_list:
-#  - ExampleDCO
 
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "sram_compiler"
 ## You should specify a location for the SRAM generator in the tech plugin
-vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"]
+vlsi.core.sram_generator_tool_path: [
+  "hammer/src/hammer-vlsi/technology/nangate45"]
 vlsi.core.sram_generator_tool_path_meta: "append"
 
+#----------------------
 # Tool options. Replace with your tool plugin of choice.
-# yosys options
+#----------------------
+
+# OpenROAD-yosys options
 vlsi.core.synthesis_tool: "yosys"
 vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"]
 vlsi.core.synthesis_tool_path_meta: "append"
 
-# Innovus options
-#vlsi.core.par_tool: "innovus"
-#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
-#vlsi.core.par_tool_path_meta: "append"
-#par.innovus.version: "181"
-#par.innovus.design_flow_effort: "standard"
-#par.inputs.gds_merge: true
-## Calibre options
-#vlsi.core.drc_tool: "calibre"
+# OpenROAD-par options
+vlsi.core.par_tool: "openroad"
+vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"]
+vlsi.core.par_tool_path_meta: "append"
+
+## OpenROAD-drc options (no lvs)
+#vlsi.core.drc_tool: "openroad"
 #vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
-#vlsi.core.lvs_tool: "calibre"
-#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi
index f853a1ed..550b56c5 100755
--- a/vlsi/example-vlsi
+++ b/vlsi/example-vlsi
@@ -1,4 +1,8 @@
 #!/usr/bin/env python3
+#
+# NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are
+# only used for asap7 though.
+
 import os
 
 import hammer_vlsi
@@ -7,21 +11,24 @@ from hammer_vlsi import CLIDriver, HammerToolHookAction
 from typing import Dict, Callable, Optional, List
 
 def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # TODO
 # Place custom TCL here
 ''')
     return True
 
 def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # TODO
 # Place custom TCL here
 ''')
     return True
 
 def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # TODO
 # Place custom TCL here
 set_db route_design_bottom_routing_layer 2
@@ -34,7 +41,8 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
     Scale the final GDS by a factor of 4
     hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script
     """
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # Write script out to a temporary file and execute it
 set fp [open "{script_file}" "w"]
 puts -nonewline $fp "{script_text}"
diff --git a/vlsi/example-vlsi-nangate45 b/vlsi/example-vlsi-nangate45
deleted file mode 100755
index 39b9a493..00000000
--- a/vlsi/example-vlsi-nangate45
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env python3
-import os
-
-import hammer_vlsi
-from hammer_vlsi import CLIDriver, HammerToolHookAction
-
-from typing import Dict, Callable, Optional, List
-
-def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
-    x.append("")
-    return True
-
-def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
-    x.append("")
-    return True
-
-class ExampleDriver(CLIDriver):
-    def get_extra_par_hooks(self) -> List[HammerToolHookAction]:
-        extra_hooks = [
-            # make_pre_insertion_hook will execute the custom hook before the specified step
-            hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
-
-            # make_replacement_hook will replace the specified step with a custom hook
-            hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
-        ]
-        return extra_hooks 
-
-if __name__ == '__main__':
-    ExampleDriver().main()
diff --git a/vlsi/hammer b/vlsi/hammer
index c5a3cdf8..4d431566 160000
--- a/vlsi/hammer
+++ b/vlsi/hammer
@@ -1 +1 @@
-Subproject commit c5a3cdf84987a46c91f3f879541060757bf225fb
+Subproject commit 4d431566a87bac14454c969e7073a63b86e31161