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Small renaming and cleanup

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This commit is contained in:
abejgonzalez
2020-11-06 21:00:18 -08:00
parent 9144e3c706
commit c5e8fecb5c
2 changed files with 12 additions and 12 deletions
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16
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -43,13 +43,13 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
// place all clocks in the shell
require(dp(ClockInputOverlayKey).size >= 1)
val sys_clk_placed = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput())
val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node
/*** Connect/Generate clocks ***/
// connect to the PLL that will generate multiple clocks
val harnessSysPLL = dp(PLLFactoryKey)()
harnessSysPLL := sys_clk_placed.overlayOutput.node
harnessSysPLL := sysClkNode
// create and connect to the dutClock
val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
@@ -73,7 +73,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
/*** DDR ***/
val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL))
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: ChipTop =>
@@ -82,7 +82,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
}
val ddrClient = TLClientNode(Seq(inParams.master))
ddrPlaced.overlayOutput.ddr := ddrClient
ddrNode := ddrClient
// module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this)
@@ -96,10 +96,10 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
_outer.xdc.addPackagePin(reset, "L19")
_outer.xdc.addIOStandard(reset, "LVCMOS12")
val reset_ibuf = Module(new IBUF)
reset_ibuf.io.I := reset
val resetIBUF = Module(new IBUF)
resetIBUF.io.I := reset
val sysclk: Clock = _outer.sys_clk_placed.overlayOutput.node.out.head._1.clock
val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
_outer.sdc.addAsyncPath(Seq(powerOnReset))
@@ -109,7 +109,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
case _ => false.B
}
_outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset)
_outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
// reset setup
val hReset = Wire(Reset())