Added retime annotation

This commit is contained in:
Adam Izraelevitz
2017-09-06 13:22:44 -07:00
parent 96939c9ab6
commit c5d01ba19c
2 changed files with 116 additions and 0 deletions

View File

@@ -0,0 +1,45 @@
// See LICENSE for license details.
package barstools.tapeout.transforms.retime
import chisel3.internal.InstanceId
import firrtl.PrimOps.Not
import firrtl.annotations.{Annotation, CircuitName, ModuleName, Named, ComponentName}
import firrtl.ir.{Input, UIntType, IntWidth, Module, Port, DefNode, NoInfo, Reference, DoPrim, Block, Circuit}
import firrtl.passes.Pass
import firrtl.{CircuitForm, CircuitState, LowForm, Transform}
object RetimeAnnotation {
def apply(target: ModuleName): Annotation = Annotation(target, classOf[RetimeTransform], "retime")
def unapply(a: Annotation): Option[Named] = a match {
case Annotation(m, t, "retime") if t == classOf[RetimeTransform] => Some(m)
case _ => None
}
}
class RetimeTransform extends Transform {
override def inputForm: CircuitForm = LowForm
override def outputForm: CircuitForm = LowForm
override def execute(state: CircuitState): CircuitState = {
getMyAnnotations(state) match {
case Nil => state
case seq => seq.foreach {
case RetimeAnnotation(ModuleName(module, CircuitName(_))) =>
logger.info(s"Retiming module $module")
case RetimeAnnotation(ComponentName(name, ModuleName(module, CircuitName(_)))) =>
logger.info(s"Retiming instance $module.$name")
case _ =>
throw new Exception(s"There should be RetimeAnnotations, got ${seq.mkString(" -- ")}")
}
state
}
}
}
trait RetimeLib {
self: chisel3.Module =>
def retime(component: InstanceId): Unit = {
annotate(chisel3.experimental.ChiselAnnotation(component, classOf[RetimeTransform], "retime"))
}
}