diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala
index a9dba5b0..667e5148 100644
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -141,7 +141,7 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
 
 class WithRocketICacheScratchpad extends Config((site, here, up) => {
   case RocketTilesKey => up(RocketTilesKey, site) map { r =>
-    r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000))))
+    r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000))))
   }
 })
 
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 998ccff9..3679ed07 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config}
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
+  new testchipip.WithSerialTLWidth(32) ++
   new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config(
 class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
+  new testchipip.WithSerialTLWidth(32) ++
   new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config(
 class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
+  new testchipip.WithSerialTLWidth(32) ++
   new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config(
 class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
+  new testchipip.WithSerialTLWidth(32) ++
   new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config(
 class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
+  new testchipip.WithSerialTLWidth(32) ++
   new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config(
 class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
+  new testchipip.WithSerialTLWidth(32) ++
   new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index 8fc51640..449354c2 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485
+Subproject commit 449354c27bf07ccc865dc6c005df1d08eaf5b01c
diff --git a/generators/testchipip b/generators/testchipip
index 39ed56be..6572beb0 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 39ed56be3e72ce09f64889b9d63c8b9fd98eb726
+Subproject commit 6572beb03bc6eb0575269eaf4cc960b72b3ddef3