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Update FPGA makefile | Reorg firtool args

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This commit is contained in:
abejgonzalez
2022-10-13 17:52:58 -07:00
committed by joey0320
parent 9f2fd22cc0
commit c472e22223
2 changed files with 11 additions and 10 deletions
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11
common.mk
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@@ -190,19 +190,20 @@ $(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
$(EXTRA_FIRRTL_OPTIONS)) $(EXTRA_FIRRTL_OPTIONS))
$(if $(shell grep "Fixed<" $(FIRRTL_FILE)),mv $(SFC_FIRRTL_BASENAME).mid.fir $(SFC_FIRRTL_FILE),) $(if $(shell grep "Fixed<" $(FIRRTL_FILE)),mv $(SFC_FIRRTL_BASENAME).mid.fir $(SFC_FIRRTL_FILE),)
firtool \ firtool \
--format=fir \
-O=release \
--dedup \
--export-module-hierarchy \ --export-module-hierarchy \
--emit-metadata \ --emit-metadata \
--format=fir \ --verify-each=false \
-warn-on-unprocessed-annotations \
-verify-each=false \
-dedup \
--annotation-file=$(SFC_ANNO_FILE) \
--disable-annotation-classless \ --disable-annotation-classless \
--disable-annotation-unknown \ --disable-annotation-unknown \
--warn-on-unprocessed-annotations \
--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \ --lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
--repl-seq-mem \ --repl-seq-mem \
--repl-seq-mem-circuit=$(MODEL) \ --repl-seq-mem-circuit=$(MODEL) \
--repl-seq-mem-file=$(FIRTOOL_SMEMS_CONF) \ --repl-seq-mem-file=$(FIRTOOL_SMEMS_CONF) \
--annotation-file=$(SFC_ANNO_FILE) \
--split-verilog \ --split-verilog \
-o $(OUT_DIR) \ -o $(OUT_DIR) \
$(SFC_FIRRTL_FILE) $(SFC_FIRRTL_FILE)

10
fpga/Makefile
View File

@@ -94,13 +94,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
# copy files but ignore *.h files in *.f (match vcs) # copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir) $(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(build_dir) cp -f $^ $(OUT_DIR)
$(foreach file,\ $(foreach file,\
$^,\ $^,\
$(if $(filter %.h,$(file)),\ $(if $(filter %.h,$(file)),\
,\ ,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
######################################################################################### #########################################################################################
# import other necessary rules and variables # import other necessary rules and variables
@@ -111,8 +111,8 @@ include $(base_dir)/common.mk
# copy from other directory # copy from other directory
######################################################################################### #########################################################################################
all_vsrcs := \ all_vsrcs := \
$(sim_vsrcs) \ $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
######################################################################################### #########################################################################################
# vivado rules # vivado rules