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Update FPGA makefile | Reorg firtool args

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This commit is contained in:
abejgonzalez
2022-10-13 17:52:58 -07:00
committed by joey0320
parent 9f2fd22cc0
commit c472e22223
2 changed files with 11 additions and 10 deletions
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10
fpga/Makefile
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@@ -94,13 +94,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
# copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(OUT_DIR)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
#########################################################################################
# import other necessary rules and variables
@@ -111,8 +111,8 @@ include $(base_dir)/common.mk
# copy from other directory
#########################################################################################
all_vsrcs := \
$(sim_vsrcs) \
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
#########################################################################################
# vivado rules