Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework

.circleci/config.yml

@@ -439,10 +439,20 @@ jobs:
 # Order and dependencies of jobs to run
 workflows:
     version: 2
+    submodules-on-master:
+        jobs:
+            # Check to make sure submodule commits are on master branches
+            - commit-on-master-check
+        triggers:
+            - schedule:
+                cron: "0 0 * * *"
+                filters:
+                    branches:
+                        only:
+                            - master
+
     build-and-test-chipyard-integration:
         jobs:
-            # check to make sure commits are on master
-            - commit-on-master-check
 
             # Make the toolchains
             - install-riscv-toolchain

.circleci/defaults.sh

@@ -38,7 +38,7 @@ declare -A mapping
 mapping["example"]="SUB_PROJECT=example"
 mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig"
 mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig"
-mapping["boom"]="SUB_PROJECT=boom"
+mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
 mapping["rocketchip"]="SUB_PROJECT=rocketchip"
 mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice"
 mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha"

.gitignore

@@ -5,6 +5,9 @@ target
 *.stamp
 *.vcd
 *.swp
+*.log
+*#
+*~
 .idea
 .DS_Store
 env.sh

.gitmodules

@@ -42,7 +42,16 @@
 	url = https://github.com/ucb-bar/esp-tools.git
 [submodule "vlsi/hammer"]
 	path = vlsi/hammer
-	url = git@github.com:ucb-bar/hammer.git
+	url = https://github.com/ucb-bar/hammer.git
 [submodule "vlsi/hammer-cad-plugins"]
 	path = vlsi/hammer-cad-plugins
-	url = git@github.com:ucb-bar/hammer-cad-plugins
+	url = https://github.com/ucb-bar/hammer-cad-plugins.git
+[submodule "tools/dsptools"]
+	path = tools/dsptools
+	url = https://github.com/ucb-bar/dsptools.git
+[submodule "tools/chisel-testers"]
+	path = tools/chisel-testers
+	url = https://github.com/freechipsproject/chisel-testers.git
+[submodule "tools/treadle"]
+	path = tools/treadle
+	url = https://github.com/freechipsproject/treadle.git

build.sbt

@@ -43,6 +43,22 @@ def conditionalDependsOn(prj: Project): Project = {
   }
 }
 
+/**
+  * It has been a struggle for us to override settings in subprojects.
+  * An example would be adding a dependency to rocketchip on midas's targetutils library,
+  * or replacing dsptools's maven dependency on chisel with the local chisel project.
+  *
+  * This function works around this by specifying the project's root at src/ and overriding
+  * scalaSource and resourceDirectory.
+  */
+def freshProject(name: String, dir: File): Project = {
+  Project(id = name, base = dir / "src")
+    .settings(
+      scalaSource in Compile := baseDirectory.value / "main" / "scala",
+      resourceDirectory in Compile := baseDirectory.value / "main" / "resources"
+    )
+}
+
 // Fork each scala test for now, to work around persistent mutable state
 // in Rocket-Chip based generators
 def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
@@ -55,6 +71,21 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
 // NB: FIRRTL dependency is unmanaged (and dropped in sim/lib)
 lazy val chisel  = (project in rocketChipDir / "chisel3")
 
+lazy val treadle = freshProject("treadle", file("tools/treadle"))
+  .settings(commonSettings)
+
+lazy val `chisel-testers` = freshProject("chisel-testers", file("./tools/chisel-testers"))
+  .dependsOn(treadle, chisel)
+  .settings(
+      commonSettings,
+      libraryDependencies ++= Seq(
+        "junit" % "junit" % "4.12",
+        "org.scalatest" %% "scalatest" % "3.0.5",
+        "org.scalacheck" %% "scalacheck" % "1.14.0",
+        "com.github.scopt" %% "scopt" % "3.7.0"
+      )
+    )
+
  // Contains annotations & firrtl passes you may wish to use in rocket-chip without
 // introducing a circular dependency between RC and MIDAS
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
@@ -66,14 +97,8 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
 lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(commonSettings)
 
-// HACK: I'm strugging to override settings in rocket-chip's build.sbt (i want
+lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-// the subproject to register a new library dependendency on midas's targetutils library)
+  .settings(commonSettings)
-// So instead, avoid the existing build.sbt altogether and specify the project's root at src/
-lazy val rocketchip = (project in rocketChipDir / "src")
-  .settings(
-    commonSettings,
-    scalaSource in Compile := baseDirectory.value / "main" / "scala",
-    resourceDirectory in Compile := baseDirectory.value / "main" / "resources")
   .dependsOn(chisel, hardfloat, rocketMacros)
 
 lazy val testchipip = (project in file("generators/testchipip"))
@@ -110,6 +135,22 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/"))
   .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
+lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
+  .dependsOn(chisel, `chisel-testers`)
+  .settings(
+      commonSettings,
+      libraryDependencies ++= Seq(
+        "org.typelevel" %% "spire" % "0.14.1",
+        "org.scalanlp" %% "breeze" % "0.13.2",
+        "junit" % "junit" % "4.12" % "test",
+        "org.scalatest" %% "scalatest" % "3.0.5" % "test",
+        "org.scalacheck" %% "scalacheck" % "1.14.0" % "test"
+  ))
+
+lazy val `rocket-dsptools` = (project in file("./tools/dsptools/rocket"))
+  .dependsOn(rocketchip, dsptools)
+  .settings(commonSettings)
+
 lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
   .dependsOn(rocketchip)
   .settings(commonSettings)

common.mk

@@ -47,16 +47,13 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_files)
 # create verilog files rules and variables
 #########################################################################################
 REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF)
-HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)
+HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF)
 
-$(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
+TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes)
-	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(TOP_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
+HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes)
-	grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_top_blackboxes)
 
-# note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time
+$(TOP_TARGETS) $(HARNESS_TARGETS): $(FIRRTL_FILE) $(ANNO_FILE)
-$(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)"
-	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
-	grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 MACROCOMPILER_MODE ?= --mode synflops
@@ -70,7 +67,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
 ########################################################################################
 # remove duplicate files in blackbox/simfiles
 ########################################################################################
-$(sim_common_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_files)
+$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
 	awk '{print $1;}' $^ | sort -u > $@
 
 #########################################################################################
@@ -96,7 +93,7 @@ run-binary-fast: $(sim)
 # helper rules to run simulator with as much debug info as possible
 #########################################################################################
 run-binary-debug: $(sim_debug)
-	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out)
+	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out)
 
 run-fast: run-asm-tests-fast run-bmark-tests-fast
 
@@ -126,30 +123,30 @@ endif
 #########################################################################################
 regression-tests = \
 	rv64ud-v-fcvt \
-        rv64ud-p-fdiv \
+	rv64ud-p-fdiv \
-        rv64ud-v-fadd \
+	rv64ud-v-fadd \
-        rv64uf-v-fadd \
+	rv64uf-v-fadd \
-        rv64um-v-mul \
+	rv64um-v-mul \
-        rv64mi-p-breakpoint \
+	rv64mi-p-breakpoint \
-        rv64uc-v-rvc \
+	rv64uc-v-rvc \
-        rv64ud-v-structural \
+	rv64ud-v-structural \
-        rv64si-p-wfi \
+	rv64si-p-wfi \
-        rv64um-v-divw \
+	rv64um-v-divw \
-        rv64ua-v-lrsc \
+	rv64ua-v-lrsc \
-        rv64ui-v-fence_i \
+	rv64ui-v-fence_i \
-        rv64ud-v-fcvt_w \
+	rv64ud-v-fcvt_w \
-        rv64uf-v-fmin \
+	rv64uf-v-fmin \
-        rv64ui-v-sb \
+	rv64ui-v-sb \
-        rv64ua-v-amomax_d \
+	rv64ua-v-amomax_d \
-        rv64ud-v-move \
+	rv64ud-v-move \
-        rv64ud-v-fclass \
+	rv64ud-v-fclass \
-        rv64ua-v-amoand_d \
+	rv64ua-v-amoand_d \
-        rv64ua-v-amoxor_d \
+	rv64ua-v-amoxor_d \
-        rv64si-p-sbreak \
+	rv64si-p-sbreak \
-        rv64ud-v-fmadd \
+	rv64ud-v-fmadd \
-        rv64uf-v-ldst \
+	rv64uf-v-ldst \
-        rv64um-v-mulh \
+	rv64um-v-mulh \
-        rv64si-p-dirty
+	rv64si-p-dirty
 
 .PHONY: run-regression-tests run-regression-tests-fast run-regression-tests-debug
 run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))

docs/Advanced-Usage/DTM-Debugging.rst

@@ -0,0 +1,50 @@
+Debugging with DTM/JTAG
+===============================
+
+By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core.
+Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation).
+TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM 
+executes a small loop of code to write the test binary byte-wise into memory.
+However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system.
+
+Creating a DTM/JTAG Config
+-------------------------------------------
+
+First, a DTM config must be created for the system that you want to create.
+This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG.
+
+.. code-block:: scala
+
+    class DTMBoomConfig extends Config(
+      new WithDTMBoomRocketTop ++
+      new WithBootROM ++
+      new WithJtagDTM ++
+      new boom.common.SmallBoomConfig)
+
+In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM.
+The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
+The rest of the mixins specify the rest of the system (cores, accelerators, etc).
+
+Starting the DTM Simulation
+-------------------------------------------
+
+After creating the config, call the ``make`` command like the following:
+
+.. code-block:: bash
+
+    cd sims/verilator
+    # or
+    cd sims/vcs
+
+    make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM
+
+In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
+After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!
+
+Debugging with JTAG
+-------------------------------------------------------
+
+Please refer to the following resources on how to debug with JTAG.
+
+* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb
+* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb

docs/Advanced-Usage/Resources.rst

@@ -0,0 +1,38 @@
+Accessing Scala Resources
+===============================
+
+A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``setResource`` or ``addResource`` functions given by FIRRTL.
+They can be used in the following way:
+
+.. code-block:: scala
+
+    class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource {
+      val io = IO(new Bundle {
+        val clock = Input(Clock())
+        val reset = Input(Bool())
+        val serial = Flipped(new SerialIO(w))
+        val exit = Output(Bool())
+      })
+
+      setResource("/testchipip/vsrc/SimSerial.v")
+      setResource("/testchipip/csrc/SimSerial.cc")
+    }
+
+In this example, the ``SimSerial`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder.
+The ``set/addResource`` path retrieves resources from the ``src/main/resources`` directory.
+So to get an item at ``src/main/resources/fileA.v`` you can use ``setResource("/fileA.v")``.
+However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath.
+Thus, you need to add the SBT project as a dependency to the FIRRTL compiler in the Chipyard ``build.sbt``, which in Chipyards case is the ``tapeout`` project.
+For example, you added a new project called ``myAwesomeAccel`` in the Chipyard ``build.sbt``.
+Then you can add it as a ``dependsOn`` dependency to the ``tapeout`` project.
+For example:
+
+.. code-block:: scala
+
+    lazy val myAwesomeAccel = (project in file("generators/myAwesomeAccelFolder"))
+      .dependsOn(rocketchip)
+      .settings(commonSettings)
+
+    lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
+      .dependsOn(myAwesomeAccel)
+      .settings(commonSettings)

docs/Advanced-Usage/index.rst

@@ -6,6 +6,7 @@ They expect you to know about Chisel, Parameters, Configs, etc.
 
 .. toctree::
    :maxdepth: 2
-   :caption: Getting Started:
+   :caption: Advanced Usage:
 
-   Heterogeneous-SoCs
+   DTM-Debugging
+   Resources

docs/Chipyard-Basics/Building-A-Chip.rst

@@ -0,0 +1,6 @@
+.. _build-a-chip:
+
+Building A Chip
+==============================
+
+TODO

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -1,4 +1,6 @@
-Chipyard Basics
+.. _chipyard-components:
+
+Chipyard Components
 ===============================
 
 Generators

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -8,8 +8,8 @@ After cloning this repo, you will need to initialize all of the submodules.
 
 .. code-block:: shell
 
-    git clone https://github.com/ucb-bar/project-template.git
+    git clone https://github.com/ucb-bar/chipyard.git
-    cd project-template
+    cd chipyard
     ./scripts/init-submodules-no-riscv-tools.sh
 
 Building a Toolchain
@@ -26,7 +26,7 @@ But to get a basic installation, just the following steps are necessary.
 
     # OR
 
-    ./scripts/build-toolchains.sh hwacha # for a hwacha modified risc-v toolchain
+    ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions
 
 Once the script is run, a ``env.sh`` file is emitted at sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables.
 You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables.

docs/Chipyard-Basics/index.rst

@@ -0,0 +1,24 @@
+Chipyard Basics
+================================
+
+These guides will walk you through the basics of the Chipyard framework:
+
+- First, we will go over the components of the framework.
+
+- Next, we will go over the different configurations available.
+
+- Then, we will go over initial framework setup.
+
+- Finally, we will briefly walk through what you can do with the Chipyard tools.
+
+Hit next to get started!
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Chipyard Basics:
+
+   Chipyard-Components
+   Configs-Parameters-Mixins
+   Initial-Repo-Setup
+   Running-A-Simulation
+   Building-A-Chip

docs/Customization/Adding-An-Accelerator.rst

@@ -1,3 +1,5 @@
+.. _adding-an-accelerator:
+
 Adding An Accelerator/Device
 ===============================
 
@@ -49,7 +51,7 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file.
 
 .. code-block:: scala
 
-    lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip)
+    lazy val yourproject = (project in file("generators/yourproject")).settings(commonSettings).dependsOn(rocketchip)
 
 You can then import the classes defined in the submodule in a new project if
 you add it as a dependency. For instance, if you want to use this code in
@@ -62,6 +64,12 @@ the ``example`` project, change the final line in build.sbt to the following.
 Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the Chipyard top level.
 This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files.
 
+.. code-block:: shell
+
+     PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache example yourproject) \
+		 $(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils)
+
+
 MMIO Peripheral
 ------------------
 

docs/Customization/Memory-Hierarchy.rst

@@ -0,0 +1,4 @@
+Memory Hierarchy
+===============================
+TODO: Talk about SiFive Cache, and integration with L1 and backing main memory models
+(maybe even Tilelink)

docs/Customization/index.rst

@@ -0,0 +1,18 @@
+Customization
+================================
+
+These guides will walk you through customization of your system-on-chip:
+
+- Contructing heterogenous systems-on-chip using the Chipyard generators and configuration system.
+
+- Adding custom accelerators to your system-on-chip.
+
+Hit next to get started!
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Customization:
+
+   Heterogeneous-SoCs
+   Adding-An-Accelerator
+   Memory-Hierarchy

docs/Getting-Started/index.rst

@@ -1,21 +0,0 @@
-Getting Started
-================================
-
-These guides will walk you through the basics of the Chipyard framework:
-
-- First, we will go over the different configurations available.
-
-- Then, we will walk through adding a custom accelerator.
-
-Hit next to get started!
-
-.. toctree::
-   :maxdepth: 2
-   :caption: Getting Started:
-
-   Chipyard-Basics
-   Configs-Parameters-Mixins
-   Adding-An-Accelerator-Tutorial
-   Initial-Repo-Setup
-   Running-A-Simulation
-   Chipyard-Generator-Mixins

docs/Quick-Start.rst

@@ -0,0 +1,49 @@
+Quick Start
+===============================
+
+Setting up the Chipyard Repo
+-------------------------------------------
+
+Start by fetching Chipyard's sources. Run:
+
+.. code-block:: shell
+
+    git clone https://github.com/ucb-bar/chipyard.git
+    cd chipyard
+    ./scripts/init-submodules-no-riscv-tools.sh
+
+This will have initialized the git submodules.
+
+Installing the RISC-V Tools
+-------------------------------------------
+
+We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure.
+This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``.
+To build the toolchains, you should run:
+
+.. code-block:: shell
+
+    ./scripts/build-toolchains.sh
+
+.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchains by adding the ``esp-tools`` argument to the script above.
+  If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain.
+
+
+What's Next?
+-------------------------------------------
+
+This depends on what you are planning to do with Chipyard.
+
+* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`.
+
+* If you intend to build one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions.
+
+* If you intend to add a new accelerator, go to :ref:`adding-an-accelerator` and follow the instructions.
+
+* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions.
+
+* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to <> and follow the instructions.
+
+* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions.
+
+* If you intend to run a VLSI flow using one of the vanilla Chipyard examples, go to <> and follow the instructions.

docs/Simulation/FPGA-Accelerated-Simulators.rst

@@ -1,3 +1,5 @@
+.. _firesim-sim-intro:
+
 FPGA-Accelerated Simulators
 ==============================
 
@@ -50,8 +52,39 @@ cannot build a FireSim simulator from any generator project in Chipyard except `
 which properly invokes MIDAS on the target RTL.
 
 In the interim, workaround this limitation by importing Config and Module
-classes from other generator projects into FireChip. You should then be able to
+classes from other generator projects into FireChip. For example, assuming you Chipyard
-refer to those classes or an alias of them in  your ``DESIGN`` or ``TARGET_CONFIG``
+config looks as following:
+
+.. code-block:: scala
+
+  class CustomConfig extends Config(
+    new WithInclusiveCache ++
+    new myproject.MyCustomConfig ++
+    new DefaultRocketConfig
+  )
+
+Then the equivalent FireChip config (in `generators/firechip/src/main/scala/TargetConfigs.scala`) based on `FireSimRocketChipConfig`
+will look as follows:
+
+.. code-block:: scala
+
+  class FireSimCustomConfig extends Config(
+    new WithBootROM ++
+    new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
+    new WithExtMemSize(0x400000000L) ++ // 16GB
+    new WithoutTLMonitors ++
+    new WithUARTKey ++
+    new WithNICKey ++
+    new WithBlockDevice ++
+    new WithRocketL2TLBs(1024) ++
+    new WithPerfCounters ++
+    new WithoutClockGating ++
+    new WithInclusiveCache ++
+    new myproject.MyCustomConfig ++
+    new freechips.rocketchip.system.DefaultConfig)
+
+
+You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG``
 variables. Note that if your target machine has I/O not provided in the default
 FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need
 to write a custom endpoint.

docs/Simulation/Software-RTL-Simulators.rst

@@ -1,3 +1,5 @@
+.. _sw-rtl-sim-intro:
+
 Software RTL Simulators
 ===================================
 

docs/Tools/Chisel-Testers.rst

@@ -0,0 +1,6 @@
+Chisel Testers
+==============================
+
+`Chisel testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs.
+It provides a Scala API for interacting with a DUT.
+It can use multiple backends, including :ref:`Treadle` and Verilator.

docs/Tools/Dsptools.rst

@@ -0,0 +1,15 @@
+Dsptools
+===============================
+
+`Dsptools <https://github.com/ucb-bar/dsptools/>`__ is a Chisel library for writing custom signal processing hardware.
+Additionally, dsptools is useful for integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
+
+Some features:
+
+* Complex type
+* Typeclasses for writing polymorphic hardware generators
+  * For example, write one FIR filter generator that works for real or complex inputs
+* Extensions to Chisel testers for fixed point and floating point types
+* A diplomatic implementation of AXI4-Stream
+* Models for verifying APB, AXI-4, and TileLink interfaces with chisel-testers
+* DSP building blocks

docs/Tools/Treadle.rst

@@ -0,0 +1,5 @@
+Treadle
+==============================
+
+`Treadle <https://github.com/freechipsproject/treadle>`__ is a circuit simulator that directly executes FIRRTL.
+It is especially useful for interactive debugging and small unit tests that benefit from a low-overhead simulator.

docs/Tools/index.rst

@@ -10,5 +10,8 @@ The following pages will introduce them, and how we can use them in order to gen
 
    Chisel
    FIRRTL
+   Treadle
+   Chisel-Testers
+   Dsptools
    Barstools
 

docs/VLSI/HAMMER.rst

@@ -1,7 +1,58 @@
-HAMMER
+Core HAMMER
 ================================
 
 `HAMMER <https://github.com/ucb-bar/hammer>`__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs.
 HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
 
 For more information, read the `HAMMER paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__.
+
+Actions
+-------
+
+Actions are the top-level tasks Hammer is capable of executing (e.g. synthesis, place-and-route, etc.)
+
+Steps
+-------
+
+Steps are the sub-components of actions that individually addressable in Hammer (e.g. placement in the place-and-route action).
+
+Hooks
+-------
+
+Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration.
+
+Tool Plugins
+============
+
+Hammer supports separately managed plugins for different CAD tool vendors.
+The types of tools (in there hammer names) supported currently include:
+
+* synthesis
+* par
+* drc
+* lvs
+* sram_generator
+* pcb
+
+In order to configure your tool plugin of choice, you will need to set several configuration variables.
+First, you should select which specific tool you want to use by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool.
+For example ``vlsi.core.par_tool: "innovus"``.
+You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
+This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifying the default values for any tool specific variables.
+In addition you can also customize the version of the tools you use by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
+Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool.
+
+The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support.
+This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``.
+
+Technology Plugins
+==================
+
+Hammer supports separately managed plugins for different technologies.
+
+Configuration
+=============
+
+To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs.
+
+You can see the current set of all available Hammer APIs `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.

docs/VLSI/index.rst

@@ -1,11 +1,11 @@
-VLSI Production
+VLSI Flow
 ================================
 
-The Chipyard framework aim to provide wrappers to a general VLSI flow.
+The Chipyard framework aims to provide wrappers for a general VLSI flow.
-In particular, we aim to support the HAMMER flow.
+In particular, we aim to support the HAMMER physical design generator flow.
 
 .. toctree::
    :maxdepth: 2
-   :caption: VLSI Production:
+   :caption: VLSI Flow:
 
    HAMMER

docs/index.rst

@@ -8,14 +8,16 @@ Welcome to Chipyard's documentation!
 
 Chipyard is a a framework for designing and evaluating full-system hardware using agile teams.
 It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip.
-New to Chipyard? Jump to the :ref:`Getting Started` page for more info.
+New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info.
+
+.. include:: Quick-Start.rst
 
 .. toctree::
    :maxdepth: 3
    :caption: Contents:
    :numbered:
 
-   Getting-Started/index
+   Chipyard-Basics/index
 
    :maxdepth: 3
    :caption: Simulation:
@@ -37,11 +39,18 @@ New to Chipyard? Jump to the :ref:`Getting Started` page for more info.
    :numbered:
    VLSI/index
 
+   :maxdepth: 3
+   :caption: Customization:
+   :numbered:
+   Customization/index
+
    :maxdepth: 3
    :caption: Advanced Usage:
    :numbered:
    Advanced-Usage/index
 
+
+
 Indices and tables
 ==================
 

generators/example/src/main/scala/BoomConfigs.scala

@@ -0,0 +1,90 @@
+package example
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.subsystem.{WithJtagDTM}
+
+import boom.common._
+
+// ---------------------
+// BOOM Configs
+// ---------------------
+
+class SmallBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallBoomConfig)
+
+class MediumBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.MediumBoomConfig)
+
+class LargeBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.LargeBoomConfig)
+
+class MegaBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.MegaBoomConfig)
+
+class jtagSmallBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.SmallBoomConfig)
+
+class jtagMediumBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.MediumBoomConfig)
+
+class jtagLargeBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.LargeBoomConfig)
+
+class jtagMegaBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.MegaBoomConfig)
+
+class SmallDualBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallDualBoomConfig)
+
+class TracedSmallBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.TracedSmallBoomConfig)
+
+class SmallRV32UnifiedBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallRV32UnifiedBoomConfig)
+
+// --------------------------
+// BOOM + Rocket Configs
+// --------------------------
+
+class SmallBoomAndRocketConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallBoomAndRocketConfig)
+
+class MediumBoomAndRocketConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.MediumBoomAndRocketConfig)
+
+class DualMediumBoomAndDualRocketConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.DualMediumBoomAndDualRocketConfig)

generators/example/src/main/scala/ConfigMixins.scala

@@ -58,6 +58,15 @@ class WithNormalBoomRocketTop extends Config((site, here, up) => {
   }
 })
 
+/**
+ * Class to specify a top level BOOM and/or Rocket system with DTM
+ */
+class WithDTMBoomRocketTop extends Config((site, here, up) => {
+  case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
+    Module(LazyModule(new BoomRocketTopWithDTM()(p)).module)
+  }
+})
+
 /**
  * Class to specify a top level BOOM and/or Rocket system with PWM
  */

generators/example/src/main/scala/Configs.scala

@@ -77,11 +77,11 @@ class HwachaL2Config extends Config(
 
 class BaseBoomConfig extends Config(
   new WithBootROM ++
-  new boom.system.LargeBoomConfig)
+  new boom.common.LargeBoomConfig)
 
 class SmallBaseBoomConfig extends Config(
   new WithBootROM ++
-  new boom.system.SmallBoomConfig)
+  new boom.common.SmallBoomConfig)
 
 class DefaultBoomConfig extends Config(
   new WithNormalBoomRocketTop ++
@@ -132,7 +132,7 @@ class DualCoreBoomConfig extends Config(
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.system.BaseConfig)
 
@@ -142,14 +142,14 @@ class DualCoreSmallBoomConfig extends Config(
   new boom.common.WithRVC ++
   new boom.common.WithSmallBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.system.BaseConfig)
 
 class RV32UnifiedBoomConfig extends Config(
   new WithNormalBoomRocketTop ++
   new WithBootROM ++
-  new boom.system.SmallRV32UnifiedBoomConfig)
+  new boom.common.SmallRV32UnifiedBoomConfig)
 
 class BoomL2Config extends Config(
   new WithInclusiveCache ++
@@ -161,22 +161,22 @@ class BoomL2Config extends Config(
 
 class BaseBoomAndRocketConfig extends Config(
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(1) ++
+  new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
 class SmallBaseBoomAndRocketConfig extends Config(
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithRVC ++
   new boom.common.WithSmallBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(1) ++
+  new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
@@ -223,11 +223,11 @@ class GPIOBoomAndRocketConfig extends Config(
 class DualCoreBoomAndOneRocketConfig extends Config(
   new WithNormalBoomRocketTop ++
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
@@ -237,12 +237,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config(
   new WithBootROM ++
   new WithMultiRoCC ++
   new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
-  new boom.system.WithRenumberHarts(rocketFirst = true) ++
+  new boom.common.WithRenumberHarts(rocketFirst = true) ++
   new hwacha.DefaultHwachaConfig ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
@@ -250,12 +250,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config(
 class RV32BoomAndRocketConfig extends Config(
   new WithNormalBoomRocketTop ++
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithBoomRV32 ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(1) ++
+  new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithRV32 ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++

generators/example/src/main/scala/Generator.scala

@@ -5,8 +5,6 @@ import chisel3._
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
 
-import boom.system.{BoomTilesKey, TestSuiteHelper}
-
 object Generator extends GeneratorApp {
   // add unique test suites
   override def addTestSuites {

generators/example/src/main/scala/TestHarness.scala

@@ -8,14 +8,19 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.util.GeneratorApp
+import freechips.rocketchip.devices.debug.{Debug}
 
-// --------------------------
+// -------------------------------
 // BOOM and/or Rocket Test Harness
-// --------------------------
+// -------------------------------
 
 case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
+case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]]
 
-class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
+/**
+ * Test harness using TSI to bringup the system
+ */
+class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
     val success = Output(Bool())
   })
@@ -24,6 +29,7 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
   override def desiredName = "TestHarness"
 
   val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
+
   dut.debug := DontCare
   dut.connectSimAXIMem()
   dut.connectSimAXIMMIO()
@@ -41,5 +47,41 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
         axi.w.bits := DontCare
     }
   })
+
   io.success := dut.connectSimSerial()
 }
+
+/**
+ * Test harness using the Debug Test Module (DTM) to bringup the system
+ */
+class TestHarnessWithDTM(implicit p: Parameters) extends Module
+{
+  val io = IO(new Bundle {
+    val success = Output(Bool())
+  })
+
+  // force Chisel to rename module
+  override def desiredName = "TestHarness"
+
+  val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p)
+
+  dut.reset := reset.asBool | dut.debug.ndreset
+  dut.connectSimAXIMem()
+  dut.connectSimAXIMMIO()
+  dut.dontTouchPorts()
+  dut.tieOffInterrupts()
+  dut.l2_frontend_bus_axi4.foreach(axi => {
+    axi.tieoff()
+    experimental.DataMirror.directionOf(axi.ar.ready) match {
+      case core.ActualDirection.Input =>
+        axi.r.bits := DontCare
+        axi.b.bits := DontCare
+      case core.ActualDirection.Output =>
+        axi.aw.bits := DontCare
+        axi.ar.bits := DontCare
+        axi.w.bits := DontCare
+    }
+  })
+
+  Debug.connectDebug(dut.debug, clock, reset.asBool, io.success)
+}

generators/example/src/main/scala/TestSuites.scala

@@ -0,0 +1,142 @@
+package example
+
+import scala.collection.mutable.{LinkedHashSet}
+
+import freechips.rocketchip.subsystem.{RocketTilesKey}
+import freechips.rocketchip.tile.{XLen}
+import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.util.{GeneratorApp}
+import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
+
+import boom.system.{BoomTilesKey}
+
+/**
+ * A set of pre-chosen regression tests
+ */
+object RegressionTestSuites
+{
+  val rv64RegrTestNames = LinkedHashSet(
+    "rv64ud-v-fcvt",
+    "rv64ud-p-fdiv",
+    "rv64ud-v-fadd",
+    "rv64uf-v-fadd",
+    "rv64um-v-mul",
+    "rv64mi-p-breakpoint",
+    "rv64uc-v-rvc",
+    "rv64ud-v-structural",
+    "rv64si-p-wfi",
+    "rv64um-v-divw",
+    "rv64ua-v-lrsc",
+    "rv64ui-v-fence_i",
+    "rv64ud-v-fcvt_w",
+    "rv64uf-v-fmin",
+    "rv64ui-v-sb",
+    "rv64ua-v-amomax_d",
+    "rv64ud-v-move",
+    "rv64ud-v-fclass",
+    "rv64ua-v-amoand_d",
+    "rv64ua-v-amoxor_d",
+    "rv64si-p-sbreak",
+    "rv64ud-v-fmadd",
+    "rv64uf-v-ldst",
+    "rv64um-v-mulh",
+    "rv64si-p-dirty")
+
+  val rv32RegrTestNames = LinkedHashSet(
+    "rv32mi-p-ma_addr",
+    "rv32mi-p-csr",
+    "rv32ui-p-sh",
+    "rv32ui-p-lh",
+    "rv32uc-p-rvc",
+    "rv32mi-p-sbreak",
+    "rv32ui-p-sll")
+}
+
+/**
+ * Helper functions to add BOOM or Rocket tests
+ */
+object TestSuiteHelper
+{
+  import freechips.rocketchip.system.DefaultTestSuites._
+  import RegressionTestSuites._
+
+  /**
+  * Add BOOM tests (asm, bmark, regression)
+  */
+  def addBoomTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(BoomTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64) {
+            TestGeneration.addSuites(env.map(rv32ud))
+          }
+        } else if (cfg.fLen >= 64) {
+          TestGeneration.addSuites(env.map(rv64ud))
+          TestGeneration.addSuites(env.map(rv64uf))
+          TestGeneration.addSuite(rv32udBenchmarks)
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        } else {
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+        }
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites(rvu.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+
+  /**
+  * Add Rocket tests (asm, bmark, regression)
+  */
+  def addRocketTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(RocketTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv32ud))
+        } else {
+          TestGeneration.addSuite(rv32udBenchmarks)
+          TestGeneration.addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv64ud))
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+}

generators/example/src/main/scala/Top.scala

@@ -12,9 +12,9 @@ import testchipip._
 
 import sifive.blocks.devices.gpio._
 
-// -------------------------------
+// ------------------------------------
 // BOOM and/or Rocket Top Level Systems
-// -------------------------------
+// ------------------------------------
 
 class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem
   with HasNoDebug
@@ -67,3 +67,12 @@ class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
 class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
   extends BoomRocketTopModule(l)
   with HasPeripheryGPIOModuleImp
+
+//---------------------------------------------------------------------------------------------------------
+
+class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem
+{
+  override lazy val module = new BoomRocketTopWithDTMModule(this)
+}
+
+class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l)

scripts/build-toolchains.sh

@@ -138,7 +138,7 @@ cd $RDIR
 echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh
 echo "export RISCV=$RISCV" >> env.sh
 echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh
-echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh
+echo "export LD_LIBRARY_PATH=$RISCV/lib\${LD_LIBRARY_PATH:+":${LD_LIBRARY_PATH}"}" >> env.sh
 echo "Toolchain Build Complete!"
 
 

scripts/firesim-setup.sh

@@ -7,12 +7,12 @@ set -o pipefail
 
 RDIR=$(pwd)
 scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
-sims_dir=$scripts_dir/../sims/
+
+cd $scripts_dir/..
 
 # Reenable the FireSim submodule
 git config --unset submodule.sims/firesim.update || true
-cd $sims_dir
+git submodule update --init sims/firesim
-git submodule update --init firesim
+cd sims/firesim
-cd firesim
 ./build-setup.sh $@ --library
 cd $RDIR

sims/vcs/Makefile

@@ -90,6 +90,7 @@ $(sim_debug) : $(sim_vsrcs) $(sim_common_files)
 #########################################################################################
 # create a vcs vpd rule
 #########################################################################################
+.PRECIOUS: $(output_dir)/%.vpd %.vpd
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	$(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $<
 

sims/verilator/Makefile

@@ -105,6 +105,7 @@ $(sim_debug): $(model_mk_debug)
 #########################################################################################
 # create a verilator vpd rule
 #########################################################################################
+.PRECIOUS: $(output_dir)/%.vpd %.vcd
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	rm -f $@.vcd && mkfifo $@.vcd
 	vcd2vpd $@.vcd $@ > /dev/null &

variables.mk

@@ -29,7 +29,7 @@ SUB_PROJECT ?= example
 
 ifeq ($(SUB_PROJECT),example)
 	SBT_PROJECT       ?= example
-	MODEL             ?= BoomRocketTestHarness
+	MODEL             ?= TestHarness
 	VLOG_MODEL        ?= TestHarness
 	MODEL_PACKAGE     ?= $(SBT_PROJECT)
 	CONFIG            ?= DefaultRocketConfig
@@ -38,18 +38,6 @@ ifeq ($(SUB_PROJECT),example)
 	TB                ?= TestDriver
 	TOP               ?= BoomRocketTop
 endif
-# for BOOM developers
-ifeq ($(SUB_PROJECT),boom)
-	SBT_PROJECT       ?= boom
-	MODEL             ?= TestHarness
-	VLOG_MODEL        ?= TestHarness
-	MODEL_PACKAGE     ?= boom.system
-	CONFIG            ?= LargeBoomConfig
-	CONFIG_PACKAGE    ?= boom.system
-	GENERATOR_PACKAGE ?= boom.system
-	TB                ?= TestDriver
-	TOP               ?= BoomRocketSystem
-endif
 # for Rocket-chip developers
 ifeq ($(SUB_PROJECT),rocketchip)
 	SBT_PROJECT       ?= rocketchip
@@ -133,7 +121,8 @@ sim_common_files           ?= $(build_dir)/sim_files.common.f
 #########################################################################################
 # java arguments used in sbt
 #########################################################################################
-JAVA_ARGS ?= -Xmx8G -Xss8M -XX:MaxPermSize=256M
+JAVA_HEAP_SIZE ?= 8G
+JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M
 
 #########################################################################################
 # default sbt launch command

vlsi/Makefile

@@ -14,109 +14,94 @@ sim_dir=$(abspath .)
 #########################################################################################
 include $(base_dir)/variables.mk
 
+#########################################################################################
+# vlsi types and rules
+#########################################################################################
+sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
+tech_name          ?=
+tech_dir           ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)
+SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
+SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
+SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
+MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
+OBJ_DIR            ?= $(vlsi_dir)/build
+ENV_YML            ?= $(vlsi_dir)/bwrc-env.yml
+INPUT_CONFS        ?= example.yml $(dir $(tech_dir))/bwrc.yml
+HAMMER_EXEC        ?= ./example-vlsi
+
+#########################################################################################
+# general rules
+#########################################################################################
+ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes)
+extra_v_includes = $(build_dir)/EICG_wrapper.v
+
+.PHONY: default verilog
+default: all
+
+all: drc lvs
+
+verilog: $(ALL_RTL)
+
 #########################################################################################
 # import other necessary rules and variables
 #########################################################################################
 include $(base_dir)/common.mk
 
 #########################################################################################
-# vlsi types and rules
+# srams
 #########################################################################################
+SRAM_GENERATOR_CONF = $(build_dir)/sram_generator-input.yml
+SRAM_CONF=$(build_dir)/sram_generator-output.json
 
-#sim_name is unused, but GenerateSimFiles expects it
+## SRAM Generator
-sim_name     ?= vcs
+.PHONY: sram_generator srams
-tech_name    ?= 
+srams: sram_generator
-tech_dir     ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)
+sram_generator: $(SRAM_CONF)
-SMEMS_COMP   ?= $(tech_dir)/sram-compiler.json
-SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
-MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER)
-OBJ_DIR      ?= $(vlsi_dir)/build
-ENV_YML      ?= $(vlsi_dir)/bwrc-env.yml
-INPUT_CONFS  ?= example.yml $(dir $(tech_dir))/bwrc.yml
-HAMMER_EXEC  ?= ./example-vlsi
 
-ROCKET_SRC_DIR=$(ROCKETCHIP_DIR)/src/main/resources/vsrc
+# This should be built alongside $(SMEMS_FILE)
+$(SMEMS_HAMMER): $(SMEMS_FILE)
 
-ROCKET_SRCS = \
+$(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER)
-	$(ROCKET_SRC_DIR)/ClockDivider2.v \
+	mkdir -p $(dir $@)
-	$(ROCKET_SRC_DIR)/ClockDivider3.v \
+	echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@
-	$(ROCKET_SRC_DIR)/AsyncResetReg.v \
+	echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@
-	$(ROCKET_SRC_DIR)/plusarg_reader.v \
-	$(ROCKET_SRC_DIR)/EICG_wrapper.v \
 
-ALL_RTL = $(ROCKET_SRCS) $(TOP_FILE) $(TOP_SMEMS_FILE)
+$(SRAM_CONF): $(SRAM_GENERATOR_CONF)
+	cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
+	cd $(vlsi_dir) && cp output.json $@
 
-CLOCK_DOMAINS = $(build_dir)/$(long_name).domains
+#########################################################################################
+# synthesis input configuration
+#########################################################################################
+SYN_CONF = $(OBJ_DIR)/inputs.yml
+GENERATED_CONFS = $(SYN_CONF) $(SRAM_CONF)
 
-.PHONY: default
+$(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes)
-default: all
-
-all: drc lvs
-
-
-###################################################### SYN ############################################################
-
-SYNTH_CONF = $(OBJ_DIR)/inputs.yml
-
-$(SYNTH_CONF):
 	mkdir -p $(dir $@)
 	echo "synthesis.inputs:" > $@
 	echo "  top_module: $(TOP)" >> $@
 	echo "  input_files:" >> $@
-	for x in $(ALL_RTL); do \
+	for x in $(ALL_RTL) $(extra_v_includes) `cat $(sim_top_blackboxes)`; do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 
-GENERATED_CONFS=$(SYNTH_CONF) $(SRAM_CONF)
+#########################################################################################
+# AUTO BUILD FLOW
+#########################################################################################
 
-.PHONY: syn synthesis
+.PHONY: buildfile
-syn: $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v
+buildfile: $(OBJ_DIR)/hammer.d
-synthesis: syn
+# Tip: Set HAMMER_D_DEPS to an empty string to avoid unnecessary RTL rebuilds
+# TODO: make this dependency smarter so that we don't need this at all
+HAMMER_D_DEPS ?= $(GENERATED_CONFS)
+$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
+	$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build
 
-$(OBJ_DIR)/syn-rundir/$(TOP).mapped.v $(OBJ_DIR)/syn-rundir/syn-output.json: $(ENV_YML) $(INPUT_CONFS) $(GENERATED_CONFS) $(ALL_RTL)
+-include $(OBJ_DIR)/hammer.d
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) syn
-
-$(OBJ_DIR)/par-input.json: $(OBJ_DIR)/syn-rundir/syn-output.json
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $<, -p $(x)) -o $@ syn_to_par
-
-###################################################### PAR ############################################################
-
-.PHONY: par place-and-route
-par: $(OBJ_DIR)/par-rundir/$(TOP).gds
-place-and-route: par
-
-$(OBJ_DIR)/par-rundir/$(TOP).gds $(OBJ_DIR)/par-rundir/par-output.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) par
-
-$(OBJ_DIR)/drc-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_drc
-
-###################################################### DRC ############################################################
-# TODO unimplemented
-.PHONY: drc
-drc: $(OBJ_DIR)/drc-rundir/drc_results.db
-
-$(OBJ_DIR)/drc-rundir/drc_results.db: $(OBJ_DIR)/drc-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) drc
-
-###################################################### LVS ############################################################
-# TODO unimplemented
-$(OBJ_DIR)/lvs-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_lvs
-
-.PHONY: lvs
-lvs: $(OBJ_DIR)/lvs-rundir/lvs_results.rpt
-
-$(OBJ_DIR)/lvs-rundir/lvs_results.rpt: $(OBJ_DIR)/lvs-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds
-	mkdir -p $(dir $@)
-	$(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) lvs
 
+#########################################################################################
+# general cleanup rule
+#########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) generated-src
+	rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir)