Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework

generators/example/src/main/scala/BoomConfigs.scala

@@ -0,0 +1,90 @@
+package example
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.subsystem.{WithJtagDTM}
+
+import boom.common._
+
+// ---------------------
+// BOOM Configs
+// ---------------------
+
+class SmallBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallBoomConfig)
+
+class MediumBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.MediumBoomConfig)
+
+class LargeBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.LargeBoomConfig)
+
+class MegaBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.MegaBoomConfig)
+
+class jtagSmallBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.SmallBoomConfig)
+
+class jtagMediumBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.MediumBoomConfig)
+
+class jtagLargeBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.LargeBoomConfig)
+
+class jtagMegaBoomConfig extends Config(
+  new WithDTMBoomRocketTop ++
+  new WithBootROM ++
+  new WithJtagDTM ++
+  new boom.common.MegaBoomConfig)
+
+class SmallDualBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallDualBoomConfig)
+
+class TracedSmallBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.TracedSmallBoomConfig)
+
+class SmallRV32UnifiedBoomConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallRV32UnifiedBoomConfig)
+
+// --------------------------
+// BOOM + Rocket Configs
+// --------------------------
+
+class SmallBoomAndRocketConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.SmallBoomAndRocketConfig)
+
+class MediumBoomAndRocketConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.MediumBoomAndRocketConfig)
+
+class DualMediumBoomAndDualRocketConfig extends Config(
+  new WithNormalBoomRocketTop ++
+  new WithBootROM ++
+  new boom.common.DualMediumBoomAndDualRocketConfig)

generators/example/src/main/scala/ConfigMixins.scala

@@ -58,6 +58,15 @@ class WithNormalBoomRocketTop extends Config((site, here, up) => {
   }
 })
 
+/**
+ * Class to specify a top level BOOM and/or Rocket system with DTM
+ */
+class WithDTMBoomRocketTop extends Config((site, here, up) => {
+  case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
+    Module(LazyModule(new BoomRocketTopWithDTM()(p)).module)
+  }
+})
+
 /**
  * Class to specify a top level BOOM and/or Rocket system with PWM
  */

generators/example/src/main/scala/Configs.scala

@@ -77,11 +77,11 @@ class HwachaL2Config extends Config(
 
 class BaseBoomConfig extends Config(
   new WithBootROM ++
-  new boom.system.LargeBoomConfig)
+  new boom.common.LargeBoomConfig)
 
 class SmallBaseBoomConfig extends Config(
   new WithBootROM ++
-  new boom.system.SmallBoomConfig)
+  new boom.common.SmallBoomConfig)
 
 class DefaultBoomConfig extends Config(
   new WithNormalBoomRocketTop ++
@@ -132,7 +132,7 @@ class DualCoreBoomConfig extends Config(
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.system.BaseConfig)
 
@@ -142,14 +142,14 @@ class DualCoreSmallBoomConfig extends Config(
   new boom.common.WithRVC ++
   new boom.common.WithSmallBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.system.BaseConfig)
 
 class RV32UnifiedBoomConfig extends Config(
   new WithNormalBoomRocketTop ++
   new WithBootROM ++
-  new boom.system.SmallRV32UnifiedBoomConfig)
+  new boom.common.SmallRV32UnifiedBoomConfig)
 
 class BoomL2Config extends Config(
   new WithInclusiveCache ++
@@ -161,22 +161,22 @@ class BoomL2Config extends Config(
 
 class BaseBoomAndRocketConfig extends Config(
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(1) ++
+  new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
 class SmallBaseBoomAndRocketConfig extends Config(
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithRVC ++
   new boom.common.WithSmallBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(1) ++
+  new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
@@ -223,11 +223,11 @@ class GPIOBoomAndRocketConfig extends Config(
 class DualCoreBoomAndOneRocketConfig extends Config(
   new WithNormalBoomRocketTop ++
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
@@ -237,12 +237,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config(
   new WithBootROM ++
   new WithMultiRoCC ++
   new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
-  new boom.system.WithRenumberHarts(rocketFirst = true) ++
+  new boom.common.WithRenumberHarts(rocketFirst = true) ++
   new hwacha.DefaultHwachaConfig ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(2) ++
+  new boom.common.WithNBoomCores(2) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
@@ -250,12 +250,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config(
 class RV32BoomAndRocketConfig extends Config(
   new WithNormalBoomRocketTop ++
   new WithBootROM ++
-  new boom.system.WithRenumberHarts ++
+  new boom.common.WithRenumberHarts ++
   new boom.common.WithBoomRV32 ++
   new boom.common.WithRVC ++
   new boom.common.WithLargeBooms ++
   new boom.common.BaseBoomConfig ++
-  new boom.system.WithNBoomCores(1) ++
+  new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithRV32 ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++

generators/example/src/main/scala/Generator.scala

@@ -5,8 +5,6 @@ import chisel3._
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
 
-import boom.system.{BoomTilesKey, TestSuiteHelper}
-
 object Generator extends GeneratorApp {
   // add unique test suites
   override def addTestSuites {

generators/example/src/main/scala/TestHarness.scala

@@ -8,14 +8,19 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.util.GeneratorApp
+import freechips.rocketchip.devices.debug.{Debug}
 
-// --------------------------
+// -------------------------------
 // BOOM and/or Rocket Test Harness
-// --------------------------
+// -------------------------------
 
 case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
+case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]]
 
-class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
+/**
+ * Test harness using TSI to bringup the system
+ */
+class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
     val success = Output(Bool())
   })
@@ -24,6 +29,7 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
   override def desiredName = "TestHarness"
 
   val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
+
   dut.debug := DontCare
   dut.connectSimAXIMem()
   dut.connectSimAXIMMIO()
@@ -41,5 +47,41 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
         axi.w.bits := DontCare
     }
   })
+
   io.success := dut.connectSimSerial()
 }
+
+/**
+ * Test harness using the Debug Test Module (DTM) to bringup the system
+ */
+class TestHarnessWithDTM(implicit p: Parameters) extends Module
+{
+  val io = IO(new Bundle {
+    val success = Output(Bool())
+  })
+
+  // force Chisel to rename module
+  override def desiredName = "TestHarness"
+
+  val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p)
+
+  dut.reset := reset.asBool | dut.debug.ndreset
+  dut.connectSimAXIMem()
+  dut.connectSimAXIMMIO()
+  dut.dontTouchPorts()
+  dut.tieOffInterrupts()
+  dut.l2_frontend_bus_axi4.foreach(axi => {
+    axi.tieoff()
+    experimental.DataMirror.directionOf(axi.ar.ready) match {
+      case core.ActualDirection.Input =>
+        axi.r.bits := DontCare
+        axi.b.bits := DontCare
+      case core.ActualDirection.Output =>
+        axi.aw.bits := DontCare
+        axi.ar.bits := DontCare
+        axi.w.bits := DontCare
+    }
+  })
+
+  Debug.connectDebug(dut.debug, clock, reset.asBool, io.success)
+}

generators/example/src/main/scala/TestSuites.scala

@@ -0,0 +1,142 @@
+package example
+
+import scala.collection.mutable.{LinkedHashSet}
+
+import freechips.rocketchip.subsystem.{RocketTilesKey}
+import freechips.rocketchip.tile.{XLen}
+import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.util.{GeneratorApp}
+import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
+
+import boom.system.{BoomTilesKey}
+
+/**
+ * A set of pre-chosen regression tests
+ */
+object RegressionTestSuites
+{
+  val rv64RegrTestNames = LinkedHashSet(
+    "rv64ud-v-fcvt",
+    "rv64ud-p-fdiv",
+    "rv64ud-v-fadd",
+    "rv64uf-v-fadd",
+    "rv64um-v-mul",
+    "rv64mi-p-breakpoint",
+    "rv64uc-v-rvc",
+    "rv64ud-v-structural",
+    "rv64si-p-wfi",
+    "rv64um-v-divw",
+    "rv64ua-v-lrsc",
+    "rv64ui-v-fence_i",
+    "rv64ud-v-fcvt_w",
+    "rv64uf-v-fmin",
+    "rv64ui-v-sb",
+    "rv64ua-v-amomax_d",
+    "rv64ud-v-move",
+    "rv64ud-v-fclass",
+    "rv64ua-v-amoand_d",
+    "rv64ua-v-amoxor_d",
+    "rv64si-p-sbreak",
+    "rv64ud-v-fmadd",
+    "rv64uf-v-ldst",
+    "rv64um-v-mulh",
+    "rv64si-p-dirty")
+
+  val rv32RegrTestNames = LinkedHashSet(
+    "rv32mi-p-ma_addr",
+    "rv32mi-p-csr",
+    "rv32ui-p-sh",
+    "rv32ui-p-lh",
+    "rv32uc-p-rvc",
+    "rv32mi-p-sbreak",
+    "rv32ui-p-sll")
+}
+
+/**
+ * Helper functions to add BOOM or Rocket tests
+ */
+object TestSuiteHelper
+{
+  import freechips.rocketchip.system.DefaultTestSuites._
+  import RegressionTestSuites._
+
+  /**
+  * Add BOOM tests (asm, bmark, regression)
+  */
+  def addBoomTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(BoomTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64) {
+            TestGeneration.addSuites(env.map(rv32ud))
+          }
+        } else if (cfg.fLen >= 64) {
+          TestGeneration.addSuites(env.map(rv64ud))
+          TestGeneration.addSuites(env.map(rv64uf))
+          TestGeneration.addSuite(rv32udBenchmarks)
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        } else {
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+        }
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites(rvu.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+
+  /**
+  * Add Rocket tests (asm, bmark, regression)
+  */
+  def addRocketTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(RocketTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv32ud))
+        } else {
+          TestGeneration.addSuite(rv32udBenchmarks)
+          TestGeneration.addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv64ud))
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+}

generators/example/src/main/scala/Top.scala

@@ -12,9 +12,9 @@ import testchipip._
 
 import sifive.blocks.devices.gpio._
 
-// -------------------------------
+// ------------------------------------
 // BOOM and/or Rocket Top Level Systems
-// -------------------------------
+// ------------------------------------
 
 class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem
   with HasNoDebug
@@ -67,3 +67,12 @@ class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
 class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
   extends BoomRocketTopModule(l)
   with HasPeripheryGPIOModuleImp
+
+//---------------------------------------------------------------------------------------------------------
+
+class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem
+{
+  override lazy val module = new BoomRocketTopWithDTMModule(this)
+}
+
+class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l)