diff --git a/.github/actions/cleanup-conda/action.yml b/.github/actions/cleanup-conda/action.yml index b9aebb67..3b0fdf88 100644 --- a/.github/actions/cleanup-conda/action.yml +++ b/.github/actions/cleanup-conda/action.yml @@ -22,7 +22,7 @@ runs: echo "Skipping removal of $envname since it cannot be parsed into a date" else NUM_DIFF=$(( ( $(date +%s) - $(date --date="$ENV_DATE" +%s) )/(60*60*24) )) - if (( $NUM_DIFF > 7 )); then + if (( $NUM_DIFF > 2 )); then echo "Removing $envname since it is $NUM_DIFF days old." conda env remove -n $envname else diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 11d12599..b0f16636 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -12,9 +12,7 @@ source $SCRIPT_DIR/defaults.sh cd $LOCAL_CHIPYARD_DIR # ignore the private vlsi submodules -git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none -git config submodule.vlsi/hammer-synopsys-plugins.update none # initialize submodules and get the hashes git submodule update --init @@ -47,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") +submodules=("cva6" "boom" "ibex" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") dir="generators" branches=("master" "main" "dev") search @@ -88,7 +86,7 @@ dir="software" branches=("master" "dev") search -submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "torture") +submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture") dir="tools" branches=("master" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 103ca856..0b5502e6 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -18,6 +18,7 @@ REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_SBT_OPTS="-Dsbt.server.forcestart=true -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" + # local variables (aka within the docker container) LOCAL_CHIPYARD_DIR=$GITHUB_WORKSPACE LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator @@ -26,7 +27,8 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # CI uses temp directories with very long names # explicitly force socket creation to use /tmp to avoid name length errors # https://github.com/sbt/sbt/pull/6887 -JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX) +REMOTE_JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX) +REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index b5755d01..445c1c31 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -52,6 +52,8 @@ read -a keys <<< ${grouping[$1]} # need to set the PATH to use the new verilator (with the new verilator root) for key in "${keys[@]}" do - export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache - make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_TMP_DIR=$JAVA_TMP_DIR SBT_OPTS="$REMOTE_SBT_OPTS" ${mapping[$key]} + export COURSIER_CACHE=$REMOTE_COURSIER_CACHE + export JVM_MEMORY=10G + export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR + make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info ${mapping[$key]} done diff --git a/.github/scripts/remote-run-firesim-scala-tests.sh b/.github/scripts/remote-run-firesim-scala-tests.sh index 960d1706..70a41e27 100755 --- a/.github/scripts/remote-run-firesim-scala-tests.sh +++ b/.github/scripts/remote-run-firesim-scala-tests.sh @@ -15,6 +15,7 @@ cd $REMOTE_CHIPYARD_DIR # Run Firesim Scala Tests export FIRESIM_ENV_SOURCED=1; -export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache -JAVA_TOOL_OPTIONS="$REMOTE_JAVA_OPTS -Djava.io.tmpdir=$(mktemp -d -t cy-fsim-XXXXXXXX)" -make -C $REMOTE_FIRESIM_DIR JAVA_TOOL_OPTIONS="$JAVA_TOOL_OPTIONS" SBT_OPTS="$REMOTE_SBT_OPTS" TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]} +export COURSIER_CACHE=$REMOTE_COURSIER_CACHE +export JVM_MEMORY=10G +export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR +make -C $REMOTE_FIRESIM_DIR TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]} diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml index 22382571..5179be0f 100644 --- a/.github/workflows/chipyard-full-flow.yml +++ b/.github/workflows/chipyard-full-flow.yml @@ -78,9 +78,23 @@ jobs: run: | cd ${{ env.REMOTE_WORK_DIR }} eval "$(conda shell.bash hook)" + mkdir ${{ env.JAVA_TMP_DIR }} export MAKEFLAGS="-j32" ./build-setup.sh -f + run-cfg-finder: + name: run-cfg-finder + needs: [setup-repo] + runs-on: ferry + steps: + - name: Run config finder + run: | + cd ${{ env.REMOTE_WORK_DIR }} + eval "$(conda shell.bash hook)" + source env.sh + cd sims/verilator + make find-config-fragments + run-tutorial: name: run-tutorial needs: [setup-repo] @@ -93,6 +107,60 @@ jobs: source env.sh cd sims/verilator make verilog + - name: VLSI test + run: | + cd ${{ env.REMOTE_WORK_DIR }} + eval "$(conda shell.bash hook)" + source env.sh + + cd vlsi + + # NOTE: most conda installs are in separate conda envs because they mess up + # each other's versions (for no apparent reason) and we need the latest versions + conda config --add channels defaults + conda config --add channels litex-hub + + # installs for example-sky130.yml + conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9 + git clone https://github.com/rahulk29/sram22_sky130_macros.git + + # installs for example-openroad.yml + conda create -y --prefix ./.conda-yosys yosys=0.27_4_gb58664d44 + conda create -y --prefix ./.conda-openroad openroad=2.0_7070_g0264023b6 + conda create -y --prefix ./.conda-klayout klayout=0.28.5_98_g87e2def28 + conda create -y --prefix ./.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172 + + echo "# Tutorial configs" > tutorial.yml + echo "# pdk" > tutorial.yml + echo "technology.sky130.sky130A: $PWD/.conda-sky130/share/pdk/sky130A" >> tutorial.yml + echo "technology.sky130.sram22_sky130_macros: $PWD/sram22_sky130_macros" >> tutorial.yml + echo "" >> tutorial.yml + echo "# tools" >> tutorial.yml + echo "synthesis.yosys.yosys_bin: $PWD/.conda-yosys/bin/yosys" >> tutorial.yml + echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> tutorial.yml + echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml + echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml + echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml + echo "" >> tutorial.yml + echo "# speed up tutorial runs & declutter log output" >> tutorial.yml + echo "par.openroad.timing_driven: false" >> tutorial.yml + echo "par.openroad.write_reports: false" >> tutorial.yml + + conda config --remove channels litex-hub + conda config --remove channels defaults + + export tutorial=sky130-openroad + export EXTRA_CONFS=tutorial.yml + export VLSI_TOP=RocketTile + make buildfile + make syn + # openroad freezes during some write commands after detailed route + # so need to stop the flow & run last step separately + make par HAMMER_EXTRA_ARGS="--stop_after_step extraction" + make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction" + make drc + make lvs + cleanup: name: cleanup diff --git a/.gitignore b/.gitignore index d3cf251d..9c73c6e1 100644 --- a/.gitignore +++ b/.gitignore @@ -24,3 +24,5 @@ first-clone-setup-fast-log project/.bloop/ project/metals.sbt project/project/ +.ivy2 +.sbt diff --git a/.gitmodules b/.gitmodules index 5d4b8226..b4beb696 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,18 +31,9 @@ [submodule "tools/dsptools"] path = tools/dsptools url = https://github.com/ucb-bar/dsptools.git -[submodule "tools/chisel-testers"] - path = tools/chisel-testers - url = https://github.com/freechipsproject/chisel-testers.git [submodule "generators/sha3"] path = generators/sha3 url = https://github.com/ucb-bar/sha3.git -[submodule "vlsi/hammer-cadence-plugins"] - path = vlsi/hammer-cadence-plugins - url = https://github.com/ucb-bar/hammer-cadence-plugins.git -[submodule "vlsi/hammer-synopsys-plugins"] - path = vlsi/hammer-synopsys-plugins - url = https://github.com/ucb-bar/hammer-synopsys-plugins.git [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins url = https://github.com/ucb-bar/hammer-mentor-plugins.git diff --git a/.readthedocs.yml b/.readthedocs.yml index 0d87ad62..b5b883b5 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -5,8 +5,6 @@ build: tools: python: "mambaforge-4.10" -formats: all - sphinx: configuration: docs/conf.py diff --git a/CHANGELOG.md b/CHANGELOG.md index 9bfb8fe7..3644fa29 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,87 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.9.0] - 2023-03-23 + +Faster FIRRTL build support work CIRCT. New software support for RISC-V GCC12 and Linux 6.2. Various bumps and fixes of all submodules. + +### Added +* Add example ring-only NoC Config by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1325 +* Bump Gemmini by @hngenc, @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1276 https://github.com/ucb-bar/chipyard/pull/1326 +* Bump FireMarshal, Bump to newer RV toolchain (deprecate use of esp-tools for Gemmini) by @abejgonzalez, @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1284 https://github.com/ucb-bar/chipyard/pull/1304 https://github.com/ucb-bar/chipyard/pull/1306 https://github.com/ucb-bar/chipyard/pull/1327 https://github.com/ucb-bar/chipyard/pull/1334 https://github.com/ucb-bar/chipyard/pull/1335 https://github.com/ucb-bar/chipyard/pull/1344 https://github.com/ucb-bar/chipyard/pull/1394 https://github.com/ucb-bar/chipyard/pull/1403 https://github.com/ucb-bar/chipyard/pull/1415 +* Add support for VC707 FPGA board by @Lorilandly in https://github.com/ucb-bar/chipyard/pull/1278 +* Fail simulations on TSI errors by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1288 +* Add pre-commit support by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1294 https://github.com/ucb-bar/chipyard/pull/1310 +* Bump mempress by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1305 +* CIRCT Integration by @abejgonzalez, @joey0320 in https://github.com/ucb-bar/chipyard/pull/1239 https://github.com/ucb-bar/chipyard/pull/1312 https://github.com/ucb-bar/chipyard/pull/1372 https://github.com/ucb-bar/chipyard/pull/1396 +* Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1303 +* Spike-as-a-Tile and use for co-simulation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1307 https://github.com/ucb-bar/chipyard/pull/1323 https://github.com/ucb-bar/chipyard/pull/1360 +* Add clone-tile configs by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1322 +* New Hammer by @harrisonliew in https://github.com/ucb-bar/chipyard/pull/1324 https://github.com/ucb-bar/chipyard/pull/1368 https://github.com/ucb-bar/chipyard/pull/1374 https://github.com/ucb-bar/chipyard/pull/1369 https://github.com/ucb-bar/chipyard/pull/1410 +* Config finder `make` target by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1328 https://github.com/ucb-bar/chipyard/pull/1381 +* Arty100T board + TSI-over-UART by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1345 +* Add graphml visualization section to docs by @schwarz-em in https://github.com/ucb-bar/chipyard/pull/1387 +* Add a frag./config for MMIO only FireSim bridges by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1393 +* Add log of chisel elaboration to generated src by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1400 +* Xcelium support by @sagark in https://github.com/ucb-bar/chipyard/pull/1386 +* Bump Sodor @a0u in https://github.com/ucb-bar/chipyard/pull/1338 +* Bump Constellation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1339 + +### Changed +* remove RocketTilesKey by @SingularityKChen in https://github.com/ucb-bar/chipyard/pull/1264 +* Move setup script to scripts/, use a symlink at top-level by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1271 +* Decoupled sbus width from boom|hwacha|gemmini memory interface widths by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1273 +* Remove conda from build-toolchains-extra.sh by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1266 +* Rework build-setup | Add single-node CI by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1282 +* Switch simulators to C++17. by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1285 +* Init FPGA submodules in build-setup.sh by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1292 +* Stripped down rocket configs for FireSim testing by @t14916 in https://github.com/ucb-bar/chipyard/pull/1302 +* Add more minimal firesim configs for testing by @t14916 in https://github.com/ucb-bar/chipyard/pull/1313 +* Add workshop info to README.md by @sagark in https://github.com/ucb-bar/chipyard/pull/1314 +* Removed FireSim tests and harnesses by @nandor in https://github.com/ucb-bar/chipyard/pull/1317 +* Move boom's tracegen interface to boom submodule by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1331 +* Split up RocketConfigs.scala by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1340 +* Sky130/Openroad Tutorial Fixes by @nayiri-k in https://github.com/ucb-bar/chipyard/pull/1392 +* Testing VLSI commands for chipyard tutorial by @nayiri-k in https://github.com/ucb-bar/chipyard/pull/1395 +* Reduce test cases for noc-config in CI by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1359 +* Remove TLHelper, directly use tilelink node constructors by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1358 +* Remove chisel-testers submodule by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1378 +* Cache `.ivy2` and `.sbt` within Chipyard root directory by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1362 + +### Fixed +* Remove extra parenthesis by @odxa20 in https://github.com/ucb-bar/chipyard/pull/1261 +* Fixed typo in Initial-Repo-Setup.rst by @PisonJay in https://github.com/ucb-bar/chipyard/pull/1269 +* fix: S-interpolator for assert, assume and printf by @SingularityKChen in https://github.com/ucb-bar/chipyard/pull/1242 +* Revert "fix: S-interpolator for assert, assume and printf" by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1272 +* changelog: fixed TinyRocketArtyConfig FPGA reset signal polarity (Please Backport) by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1257 +* Fix CY logo in README by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1295 +* More files to gitignore by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1297 +* Bump rocket-dsp-utils for ShiftRegisterMem fix. by @milovanovic in https://github.com/ucb-bar/chipyard/pull/1298 +* Set VLOGMODEL=MODEL by default in variables.mk by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1337 +* Fix compile breaking due to merge conflict by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1321 +* Makefile bug fixes by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1336 +* Fix Verilog Prerequisites + Ignore `mv` stdout by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1406 +* Fix Chisel hierarchy API - Fixes #1356 by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1361 +* Remove gen-collateral when rebuilding by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1342 +* Fix VLSI input files list emission to avoid bash "too many arguments" error by @sagark in https://github.com/ucb-bar/chipyard/pull/1348 +* Small build system improvements by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1349 +* Fix socket name length issues on CI by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1353 +* Fix TestDriver.v missing from gen-collateral after recompiling by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1354 +* Consolidate CI testing configs to improve CI runtime by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1352 +* Remove Duplicate Compiler Flags by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1351 +* fpga makefile clean fix by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1357 +* Fix newline in message in build-setup.sh by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1365 +* Update assert message if configs can't be split by `:` by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1373 +* Remove Duplicate Compiler Flags by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1367 +* Move more tmp/ folders to a unique location by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1382 +* Remove stale conda env's after 2 days by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1389 +* Match CY/FireSim deps | Unpin deps | Update lockfiles by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1391 +* Only support HTML docs by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1401 +* Only HTML docs v2 by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1402 +* Fix ANSI color output by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1407 +* Fix chisel elab errors not causing flow to stop by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1409 +* lean gemmini tutorial by @sagark in https://github.com/ucb-bar/chipyard/pull/1413 + ## [1.8.1] - 2022-10-18 Various fixes and improvements, bump FireSim to 1.15.1. diff --git a/README.md b/README.md index 7e44cc11..a21b142e 100644 --- a/README.md +++ b/README.md @@ -84,6 +84,7 @@ These additional publications cover many of the internal components used in Chip * **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192). * **VLSI** * **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html). + * **Hammer**: H. Liew, et al., *DAC'22*. [PDF](https://dl.acm.org/doi/abs/10.1145/3489517.3530672). ## Acknowledgements diff --git a/common.mk b/common.mk index 54c1644e..6934df73 100644 --- a/common.mk +++ b/common.mk @@ -17,6 +17,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ +" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" @@ -25,6 +26,7 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= +ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW) #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ @@ -47,11 +49,13 @@ HELP_COMMANDS += \ " run-tests = run all assembly and benchmark tests" \ " launch-sbt = start sbt terminal" \ + ######################################################################################### # include additional subproject make fragments # see HELP_COMPILATION_VARIABLES ######################################################################################### include $(base_dir)/generators/cva6/cva6.mk +include $(base_dir)/generators/ibex/ibex.mk include $(base_dir)/generators/tracegen/tracegen.mk include $(base_dir)/generators/nvdla/nvdla.mk include $(base_dir)/tools/dromajo/dromajo.mk @@ -117,7 +121,7 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: $(GEN_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS) --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ --legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \ - $(EXTRA_CHISEL_OPTIONS)) + $(EXTRA_CHISEL_OPTIONS)) | tee $(CHISEL_LOG_FILE)) define mfc_extra_anno_contents [ @@ -167,6 +171,7 @@ SFC_MFC_TARGETS = \ $(GEN_COLLATERAL_DIR) SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) +MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket # DOC include start: FirrtlCompiler # There are two possible cases for this step. In the first case, SFC @@ -179,13 +184,18 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) # hack: lower to low firrtl if Fixed types are found # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool -$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) +$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(VLOG_SOURCES) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) else $(eval SFC_LEVEL := low) $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) +endif +ifeq (,$(ENABLE_YOSYS_FLOW)) + $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS)) +else + $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays) endif if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi @@ -203,10 +213,10 @@ $(SFC_MFC_TARGETS) &: $(BTL_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) --allow-unrecognized-annotations \ -X $(SFC_LEVEL) \ $(EXTRA_FIRRTL_OPTIONS)) - -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL - @if [ $(SFC_LEVEL) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi - @if [ $(SFC_LEVEL) = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi - @if [ $(SFC_LEVEL) = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi + -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL + @if [ $(SFC_LEVEL) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json; fi + @if [ $(SFC_LEVEL) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi + @if [ $(SFC_LEVEL) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi firtool \ --format=fir \ --dedup \ @@ -217,7 +227,7 @@ $(SFC_MFC_TARGETS) &: $(BTL_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) --disable-annotation-classless \ --disable-annotation-unknown \ --mlir-timing \ - --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ + --lowering-options=$(MFC_LOWERING_OPTIONS) \ --repl-seq-mem \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-circuit=$(MODEL) \ @@ -225,7 +235,7 @@ $(SFC_MFC_TARGETS) &: $(BTL_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) --split-verilog \ -o $(GEN_COLLATERAL_DIR) \ $(SFC_FIRRTL_FILE) - -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) + -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler @@ -380,8 +390,22 @@ launch-sbt: cd $(base_dir) && $(SBT) "$(SBT_COMMAND)" ######################################################################################### -# print help text +# print help text (and other help) ######################################################################################### +# helper to add newlines (avoid bash argument too long) +define \n + + +endef + +CONFIG_FRAG_LEVELS ?= 3 +.PHONY: find-config-fragments +find-config-fragments: private IN_F := $(shell mktemp -d -t cy-XXXXXXXX)/scala_files.f +find-config-fragments: $(SCALA_SOURCES) + @$(foreach file,$(SCALA_SOURCES),echo $(file) >> $(IN_F)${\n}) + $(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) $(IN_F) + @rm -rf $(dir $(IN_F)) + .PHONY: help help: @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 4f6f6fd3..59c5de51 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -1,6 +1,7 @@ channels: - ucb-bar - conda-forge + - litex-hub - nodefaults platforms: @@ -31,11 +32,31 @@ dependencies: - dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo - firtool==1.30.0 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock + # misc + - autoconf + - pre-commit + - readline + - coreutils + - jq + - pip + # firemarshal deps + - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock + - rsync + - psutil + - doit>=0.34.0 + - gitpython + - humanfriendly + - ctags + - bison + - flex + - expat - python>=3.9 - bc + - unzip - patch - which + - sed - diffutils - bash - gzip @@ -43,26 +64,11 @@ dependencies: - perl - tar - file + - wget - findutils - - rsync - - psutil - - doit=0.35.0 - - gitpython - - humanfriendly - - e2fsprogs - - ctags - - bison - - flex - - expat - - make - - pyyaml - - unzip - - readline - - coreutils - lzop - - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock - - jq + - make - bash-completion - sbt - ca-certificates @@ -88,48 +94,16 @@ dependencies: - elfutils - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock - conda-lock>=1 - - wget - - sed - - autoconf - - pre-commit # clang-format for driver coding style enforcement. - clang-format - clang-tools - # python packages - # While it is possible to install using pip after creating the - # conda environment, pip's dependency resolution can conflict with - # conda and create broken environments. It's best to use the conda - # packages so that the environment is consistent - - boto3==1.20.21 - - colorama==0.4.3 - - argcomplete==1.12.3 - - python-graphviz==0.19 - - pyparsing==3.0.6 - - numpy==1.19.5 - - kiwisolver==1.3.1 - - matplotlib-base==3.3.4 - - pandas==1.1.5 - - awscli==1.22.21 - - pytest==6.2.5 - - pytest-dependency==0.5.1 - - pytest-mock==3.7.0 - - moto==3.1.0 - - pyyaml==5.4.1 - - mypy==0.931 - - types-pyyaml==6.0.4 - - boto3-stubs==1.21.6 - - botocore-stubs==1.24.7 - - mypy-boto3-s3==1.21.0 - - sty==1.0.0 - - pip + # hammer packages + - sty + - open_pdks.sky130a - pip: - - fab-classic==1.19.1 - - mypy-boto3-ec2==1.21.9 - - sure==2.0.0 - - pylddwrap==1.2.1 - - hammer-vlsi[asap7]==1.0.1 + - hammer-vlsi[asap7]==1.1.0 # doc requirements - sphinx @@ -137,3 +111,45 @@ dependencies: - sphinx-autobuild - sphinx_rtd_theme - docutils + + # firesim python packages + # While it is possible to install using pip after creating the + # conda environment, pip's dependency resolution can conflict with + # conda and create broken environments. It's best to use the conda + # packages so that the environment is consistent + - colorama + - argcomplete + - python-graphviz + - pyparsing + - numpy + - kiwisolver + - matplotlib-base + - pandas + - awscli + - pytest + - pytest-dependency + - pytest-mock + - moto + - mypy + - s3fs + - aiohttp + - pip: + - sure + - pylddwrap + + # firesim ci shared packages + - boto3 + - boto3-stubs + - mypy-boto3-s3 + - mypy_boto3_ec2 + - botocore-stubs + - pytz + - types-pytz + - pyyaml + - types-pyyaml + - requests + - types-requests + - azure-identity + - fsspec + - pip: + - fab-classic>=1.19.2 diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml index 90391142..6c22731e 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml @@ -9,26 +9,24 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-circt/conda-reqs/esp-tools.yaml -f /scratch/abejgonza/chipyard/conda-reqs/chipyard.yaml -f /scratch/abejgonza/chipyard/conda-reqs/esp-tools.yaml -f /Users/joonhohwangbo/Documents/Research/coding/chipyard/conda-reqs/chipyard.yaml -f /Users/joonhohwangbo/Documents/Research/coding/chipyard/conda-reqs/esp-tools.yaml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar used_env_vars: [] - url: conda-forge used_env_vars: [] + - url: litex-hub + used_env_vars: [] - url: nodefaults used_env_vars: [] content_hash: - linux-64: a35d2d686143e59e5bd9d371d76df75404ab0fa73130fddb98354ca511b929c1 + linux-64: cee2f923f616452b736c4314db2e791c5402803fdf7a7e344bb8233950f19b67 platforms: - linux-64 sources: - - /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml - - /scratch/abejgonza/cy-circt/conda-reqs/esp-tools.yaml - - /scratch/abejgonza/chipyard/conda-reqs/chipyard.yaml - - /scratch/abejgonza/chipyard/conda-reqs/esp-tools.yaml - - /Users/joonhohwangbo/Documents/Research/coding/chipyard/conda-reqs/chipyard.yaml - - /Users/joonhohwangbo/Documents/Research/coding/chipyard/conda-reqs/esp-tools.yaml + - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml + - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml package: - category: main dependencies: {} @@ -184,6 +182,17 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-12.2.0-h46fd767_19.tar.bz2 version: 12.2.0 +- category: main + dependencies: {} + hash: + md5: 7697d37e29669a14b053e82fad22a16b + sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 + manager: conda + name: open_pdks.sky130a + optional: false + platform: linux-64 + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 + version: 1.0.402_1_g12df12e - category: main dependencies: {} hash: @@ -383,16 +392,16 @@ package: version: 1.18.1 - category: main dependencies: - libgcc-ng: '>=10.3.0' + libgcc-ng: '>=12' hash: - md5: b0929effe5b852ce3e7b2a78c2c35376 - sha256: 164bd59917902450fcc5e4ca6f12f190e08e0c39c31f20c8330b0dba865ddc5a + md5: 80968e6760b2448f739cd32b1324d07d + sha256: c8b52559c1867ad59510c9479a15581cbfda0a7857a33ff2fce03a76a0775cfb manager: conda name: coreutils optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.1-h166bdaf_0.tar.bz2 - version: '9.1' + url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.2-h0b41bf4_0.conda + version: '9.2' - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -417,18 +426,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/dromajo-1.0.0-0_h1234567_g6a6e34e.tar.bz2 version: 1.0.0 -- category: main - dependencies: - libgcc-ng: '>=10.3.0' - hash: - md5: 40e0c155eafefec2a63d1df0de0f5cdc - sha256: 1c0b56f8c25dab0a2d4db25f0209f1fe9b83539a649dd821b97c4bfbbc12c3f7 - manager: conda - name: e2fsprogs-libs - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/e2fsprogs-libs-1.46.2-h166bdaf_0.tar.bz2 - version: 1.46.2 - category: main dependencies: libgcc-ng: '>=12' @@ -481,15 +478,15 @@ package: version: 0.21.1 - category: main dependencies: - libgcc-ng: '>=7.5.0' + libgcc-ng: '>=12' hash: - md5: 626e68ae9cc5912d6adb79d318cf962d - sha256: 6ecacdbdf5cd9d2b46211b15a2f7db428ea5edd0cae9be89ccd837fc7b35643f + md5: 96f3b11872ef6fad973eac856cd2624f + sha256: 41ec165704ccce2faa0437f4f53c03c06261a2cc9ff7614828e51427d9261f4b manager: conda name: giflib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/giflib-5.2.1-h36c2ea0_2.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/giflib-5.2.1-h0b41bf4_3.conda version: 5.2.1 - category: main dependencies: @@ -579,6 +576,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/lerc-4.0.0-h27087fc_0.tar.bz2 version: 4.0.0 +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 9194c9bf9428035a05352d031462eae4 + sha256: ddc961a36d498aaafd5b71078836ad5dd247cc6ba7924157f3801a2f09b77b14 + manager: conda + name: libbrotlicommon + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlicommon-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: libgcc-ng: '>=12' @@ -639,18 +648,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2 version: '1.17' -- category: main - dependencies: - libgcc-ng: '>=12' - hash: - md5: b4f717df2d377410b462328bf0e8fb7d - sha256: 0d8b666ca4deabf948a76654df0fa1277145bed1c9e8a58e18a649c22c5f1c3e - manager: conda - name: libjpeg-turbo - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libjpeg-turbo-2.1.4-h166bdaf_0.tar.bz2 - version: 2.1.4 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -875,14 +872,14 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: e043403cd18faf815bf7705ab6c1e092 - sha256: cd981c5c18463bc7a164fcf45c5cf697d58852b780b4dfa5e83c18c1fda6d7cd + md5: 2d833be81a21128e317325a01326d36f + sha256: d378afcec34b86fef4da3ebd622b3e614cb3f71e54b6a5a10adb1d23745ecc72 manager: conda name: openssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.0.8-h0b41bf4_0.conda - version: 3.0.8 + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-h0b41bf4_0.conda + version: 3.1.0 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -1053,15 +1050,15 @@ package: version: 0.11.1 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 1e15f6ad85a7d743a2ac68dae6c82b98 - sha256: d45c4d1c8372c546711eb3863c76d899d03a67c3edb3b5c2c46c9492814cbe03 + md5: bce9f945da8ad2ae9b1d7165a64d0f87 + sha256: b8dda3b560e8a7830fe23be1c58cc41f407b2e20ae2f3b6901eb5842ba62b743 manager: conda name: xorg-xextproto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-xextproto-7.3.0-h7f98852_1002.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-xextproto-7.3.0-h0b41bf4_1003.conda version: 7.3.0 - category: main dependencies: @@ -1222,6 +1219,32 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-16_linux64_openblas.tar.bz2 version: 3.9.0 +- category: main + dependencies: + libbrotlicommon: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: 4ae4d7795d33e02bd20f6b23d91caf82 + sha256: d88ba07c3be27c89cb4975cc7edf63ee7b1c62d01f70d5c3f7efeb987c82b052 + manager: conda + name: libbrotlidec + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlidec-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 +- category: main + dependencies: + libbrotlicommon: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: 04bac51ba35ea023dc48af73c1c88c25 + sha256: a0468858b2f647f51509a32040e93512818a8f9980f20b3554cccac747bcc4be + manager: conda + name: libbrotlienc + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlienc-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1269,16 +1292,16 @@ package: libgcc-ng: '>=12' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' - openssl: '>=3.0.7,<4.0a0' + openssl: '>=3.0.8,<4.0a0' hash: - md5: dd682f0b6d65e75b2bc868fc8e93d87e - sha256: acb80dfd0b7be38c47101df812fc903374c8408daec127edb6f11a648a67c243 + md5: 613955a50485812985c059e7b269f42e + sha256: ecd6b08c2b5abe7d1586428c4dd257dcfa00ee53700d79cdc8bca098fdfbd79a manager: conda name: libnghttp2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libnghttp2-1.51.0-hff17c54_0.conda - version: 1.51.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libnghttp2-1.52.0-h61bc06f_0.conda + version: 1.52.0 - category: main dependencies: libgcc-ng: '>=12' @@ -1356,13 +1379,13 @@ package: libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: 3b933ea47ef8f330c4c068af25fcd6a8 - sha256: b30713fb4477ff4f722280d956593e7e7a2cb705b7444dcc278de447432b43b1 + md5: bb808b654bdc3c783deaf107a2ffb503 + sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-h7463322_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda version: 2.10.3 - category: main dependencies: @@ -1380,16 +1403,16 @@ package: - category: main dependencies: gmp: '>=6.2.1,<7.0a0' - libgcc-ng: '>=7.5.0' + libgcc-ng: '>=12' hash: - md5: ea9ebeddb066da8fad4a815e61b139be - sha256: d2d71ac6ed3b32f06b7db2691e0a1760016ce13fb0c50a9de6ed1ccc33e35ff3 + md5: 14d87bdff2cbd3b1179a29fb316ed743 + sha256: 03097f21c75b0936471809e533dbae44af9d9ae696ecf264d1a929fc9f9e4b83 manager: conda name: mpfr optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.1.0-h9202a9a_1.tar.bz2 - version: 4.1.0 + url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.2.0-hb012696_0.conda + version: 4.2.0 - category: main dependencies: libffi: '>=3.4.2,<3.5.0a0' @@ -1591,6 +1614,20 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/bison-3.8-h9c3ff4c_0.tar.bz2 version: '3.8' +- category: main + dependencies: + libbrotlidec: 1.0.9 h166bdaf_8 + libbrotlienc: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: e5613f2bc717e9945840ff474419b8e4 + sha256: ab1994e03bdd88e4b27f9f802ac18e45ed29b92cce25e1fd86da43b89734950f + manager: conda + name: brotli-bin + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/brotli-bin-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: gcc_impl_linux-64: '>=12.2.0,<12.2.1.0a0' @@ -1773,13 +1810,13 @@ package: libzlib: '>=1.2.13,<1.3.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 70cbb0c2033665f2a7339bf0ec51a67f - sha256: 3fb9a9cfd2f5c79e8116c67f95d5a9b790ec66807ae0d8cebefc26fda9f836a7 + md5: 17d91085ccf5934ce652cb448d0cb65a + sha256: f649fac60cb122bf0d85c4955725d94c353fdbd768bcd44f0444979b363cc9ab manager: conda name: libllvm15 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm15-15.0.7-hadd5161_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libllvm15-15.0.7-hadd5161_1.conda version: 15.0.7 - category: main dependencies: @@ -1911,19 +1948,20 @@ package: version: 1.20.3 - category: main dependencies: - libgcc-ng: '>=9.3.0' - libxcb: 1.* + libgcc-ng: '>=12' + libxcb: '>=1.13,<1.14.0a0' xorg-kbproto: '' + xorg-xextproto: '>=7.3.0,<8.0a0' xorg-xproto: '' hash: - md5: 12a61e640b8894504326aadafccbb790 - sha256: ec4641131e3afcb4b34614a5fa298efb34f54c2b2960bf9a73a8d202140d47c4 + md5: ea8fbfeb976ac49cbeb594e985393514 + sha256: 3c6862a01a39cdea3870b132706ad7256824299947a3a94ae361d863d402d704 manager: conda name: xorg-libx11 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libx11-1.7.2-h7f98852_0.tar.bz2 - version: 1.7.2 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libx11-1.8.4-h0b41bf4_0.conda + version: 1.8.4 - category: main dependencies: python: '>=3.6' @@ -1952,14 +1990,14 @@ package: dependencies: python: '>=3.6' hash: - md5: f3f2ab3ce28979a24d1a988ba211eb9b - sha256: 1354731d0eb1b406b66b3cb3d6ab74d7cbe9c0ec1d30b9e5afa366d4539e4687 + md5: b3c15cb1d45fd10bc6f652bbc51e023a + sha256: 8dbc6de55113ea67a64f0be5d16ba939d1b58a25dbd9a5cc62b571cef24ef85c manager: conda - name: asn1crypto + name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/asn1crypto-1.5.1-pyhd8ed1ab_0.tar.bz2 - version: 1.5.1 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda + version: 3.0.2 - category: main dependencies: libgcc-ng: '>=12' @@ -1986,6 +2024,21 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/attrs-22.2.0-pyh71513ae_0.conda version: 22.2.0 +- category: main + dependencies: + brotli-bin: 1.0.9 h166bdaf_8 + libbrotlidec: 1.0.9 h166bdaf_8 + libbrotlienc: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: 2ff08978892a3e8b954397c461f18418 + sha256: 74c0fa22ea7c62d2c8f7a7aea03a3bd4919f7f3940ef5b027ce0dfb5feb38c06 + manager: conda + name: brotli + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/brotli-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: python: '>=3.6' @@ -2063,26 +2116,26 @@ package: dependencies: python: '' hash: - md5: 9cf68a6826504feedbfd646bc4d1ca14 - sha256: c04c09570a8bccf45bb73ae63d7e396d66c01580f9125ce5e5c981a2be549a51 + md5: c08b4c1326b880ed44f3ffb04803332f + sha256: ddf1749f0fd5a098a7954d98267cebca83a36b86719ce4ab6fc4aa94ef518432 manager: conda name: colorama optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/colorama-0.4.3-py_0.tar.bz2 - version: 0.4.3 + url: https://conda.anaconda.org/conda-forge/noarch/colorama-0.4.4-pyh9f0ad1d_0.tar.bz2 + version: 0.4.4 - category: main dependencies: python: '>=3.6,<4.0' hash: - md5: b8477552274c1cfdb533e954c76523f1 - sha256: af1db267e03c649aefcc1571ddce4eac361a0e5232d1bdd05fd93fadbfdd2da6 + md5: 709a2295dd907bb34afb57d54320642f + sha256: 2f05954a3faf0700c14c1deddc085385160ee32abe111699c78d9cb277e915cc manager: conda name: crashtest optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/crashtest-0.3.1-pyhd8ed1ab_0.tar.bz2 - version: 0.3.1 + url: https://conda.anaconda.org/conda-forge/noarch/crashtest-0.4.1-pyhd8ed1ab_0.tar.bz2 + version: 0.4.1 - category: main dependencies: python: '>=3.6' @@ -2126,14 +2179,14 @@ package: python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: eeb35a5548c9b90fcfd6b36bc013557b - sha256: b9cfde2a6a78a54f3e8e65f009cf9d6faabface5e96d66d65d278be7c577f0e5 + md5: 4f0fa7459a1f40a969aaad418b1c428c + sha256: 97110dd30d9b321b635cc1213e478f5e598ed80c7bdb674c0c7d23d6937f2dfe manager: conda name: docutils optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/docutils-0.15.2-py39hf3d152e_6.tar.bz2 - version: 0.15.2 + url: https://conda.anaconda.org/conda-forge/linux-64/docutils-0.16-py39hf3d152e_3.tar.bz2 + version: '0.16' - category: main dependencies: expat: '>=2.4.8,<3.0a0' @@ -2155,14 +2208,26 @@ package: dependencies: python: '>=3.7' hash: - md5: 1addc115923d646ca19ed90edc413506 - sha256: 739c48f62747c942aa733041d36a2c1af41c2ecf2a59f1fec90cd7200e01be9a + md5: 7312299d7a0ea4993159229b7d2dceb2 + sha256: f073c3ba993912f1c0027bc34a54975642885f0a4cd5f9dc42a17ca945df2c18 + manager: conda + name: exceptiongroup + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/exceptiongroup-1.1.1-pyhd8ed1ab_0.conda + version: 1.1.1 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 6f90f1dc834447823b11d155726fcb37 + sha256: 6a6901f20c5b4d81aebd25a0645b3578ebb6a323f9fd7e87ee05ecbcfe19069e manager: conda name: filelock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.9.0-pyhd8ed1ab_0.conda - version: 3.9.0 + url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.10.0-pyhd8ed1ab_0.conda + version: 3.10.0 - category: main dependencies: expat: '>=2.5.0,<3.0a0' @@ -2179,6 +2244,32 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/fontconfig-2.14.2-h14ed4e7_0.conda version: 2.14.2 +- category: main + dependencies: + libgcc-ng: '>=12' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 + hash: + md5: e5e0bc1285c83d925b42ad139adca58f + sha256: dbbc7345460425791271e6fc34c5ee2adcc66f18f637ff6a219880dc4375a720 + manager: conda + name: frozenlist + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/frozenlist-1.3.3-py39hb9d737c_0.tar.bz2 + version: 1.3.3 +- category: main + dependencies: + python: '>=3.8' + hash: + md5: 0db48a2f5a68e28e5af8d3df276f2255 + sha256: dfcee90620d13f4f667664620191d780c79ec7e9ba9908cd771d24a1361e0cc9 + manager: conda + name: fsspec + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.3.0-pyhd8ed1ab_1.conda + version: 2023.3.0 - category: main dependencies: jpeg: '>=9e,<10a' @@ -2314,16 +2405,16 @@ package: version: 0.8.0 - category: main dependencies: - python: '' + python: '>=3.7' hash: - md5: 5988f73e79824c7900954539fbfad3fa - sha256: f75db900a1886fc0813af806a127186506c669431b73a92600de06aadae922ae + md5: 2cfa3e1cf3fb51bb9b17acc5b5e9ea11 + sha256: 95ac5f9ee95fd4e34dc051746fc86016d3d4f6abefed113e2ede049d59ec2991 manager: conda name: jmespath optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/jmespath-0.10.0-pyh9f0ad1d_0.tar.bz2 - version: 0.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/jmespath-1.0.1-pyhd8ed1ab_0.tar.bz2 + version: 1.0.1 - category: main dependencies: python: '>=3.6' @@ -2350,33 +2441,33 @@ package: version: '2.0' - category: main dependencies: - libgcc-ng: '>=9.3.0' - libstdcxx-ng: '>=9.3.0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: c5d6241b3ec5d02c316a5f66f14024c7 - sha256: 32fa01aacf67d40b54fbcf9c7e89aae964450ffdb58bb93baba068d8b5c72c3e + md5: 41679a052a8ce841c74df1ebc802e411 + sha256: eb28254cc7029e702d0059536d986b010221de62f9c8588a5a83e95a00b4e74d manager: conda name: kiwisolver optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/kiwisolver-1.3.1-py39h1a9c180_1.tar.bz2 - version: 1.3.1 + url: https://conda.anaconda.org/conda-forge/linux-64/kiwisolver-1.4.4-py39hf939315_1.tar.bz2 + version: 1.4.4 - category: main dependencies: jpeg: '>=9e,<10a' libgcc-ng: '>=12' libtiff: '>=4.5.0,<4.6.0a0' hash: - md5: c2566c2ea5f153ddd6bf4acaf7547d97 - sha256: 632f191ac65bc673f8fcef9947e2c8431b0db6ca357ceebde3bdc4ed187af814 + md5: aa8840cdf17ef0c6084d1e24abc7a28b + sha256: 443e926b585528112ec6aa4d85bf087722914ed8d85a2f75ae47c023c55c4238 manager: conda name: lcms2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.14-hfd0df8a_1.conda - version: '2.14' + url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-hfd0df8a_0.conda + version: '2.15' - category: main dependencies: libgcc-ng: '>=12' @@ -2426,32 +2517,33 @@ package: dependencies: krb5: '>=1.20.1,<1.21.0a0' libgcc-ng: '>=12' - libnghttp2: '>=1.47.0,<2.0a0' + libnghttp2: '>=1.52.0,<2.0a0' libssh2: '>=1.10.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' - openssl: '>=3.0.7,<4.0a0' + openssl: '>=3.1.0,<4.0a0' + zstd: '>=1.5.2,<1.6.0a0' hash: - md5: bc302fa1cf8eda15c60f669b7524a320 - sha256: dbe6253906a6a1a0b0c4f26581143f4b434c58c67db78ee4adaf2c1c37bae226 + md5: 3d1189864d1c0ed2a5919cb067b5903d + sha256: 500c08e61871df6dc4fc87913c99cb799f5fa8333db991201be32b657e9dcdb1 manager: conda name: libcurl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libcurl-7.87.0-hdc1c0ab_0.conda - version: 7.87.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libcurl-7.88.1-hdc1c0ab_1.conda + version: 7.88.1 - category: main dependencies: - gnutls: '>=3.7.6,<3.8.0a0' + gnutls: '>=3.7.8,<3.8.0a0' libgcc-ng: '>=12' hash: - md5: 78ff89df42ec0d4fe4355490d7843d9b - sha256: 780c82366caab4a741f2a4baa901a9b71fad6c2b8f1f64c168f10f61a939e9d4 + md5: a946cb6b36807a772748b55f59089a08 + sha256: 33ddfa3d91816ee44df405424ee2fedf5df5c02a1ffa1819aa4c956eedae4533 manager: conda name: libmicrohttpd optional: false platform: linux-64 - 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category: main dependencies: python: '>=3.6' @@ -3843,13 +3923,13 @@ package: ruamel.yaml.clib: '>=0.1.2' setuptools: '' hash: - md5: 51ad16ab9c63e5d14145f34adbbacf70 - sha256: be03761fc9230416697e78e1a9b35af3165b03e7e8c6efa0d01157898d564741 + md5: b64be7a2bbc2acc61c1a2161512387c2 + sha256: 1dd205a1ab9897482804b5ef3f2a1cea44f01e831d1bcff439d1e0894ab0e4a9 manager: conda name: ruamel.yaml optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.21-py39hb9d737c_2.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.21-py39h72bdee0_3.conda version: 0.17.21 - category: main dependencies: @@ -3867,41 +3947,41 @@ package: - category: main dependencies: colorama: '' - python: '>=2.7' + python: '>=3.7' hash: - md5: 5526ff3f88f9db87bb0924b9ce575345 - sha256: d196e0c3a057a840147fa23d3d43eafd6b63258846bdafe8ac17f70b534f91bd + md5: ed792aff3acb977d09c7013358097f83 + sha256: b35f185a678109940d34f68ac5781c3cbda9b118b8d9886b8f68ab5be6afd4fc manager: conda name: tqdm optional: false platform: linux-64 - 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category: main dependencies: alsa-lib: '>=1.2.8,<1.2.9.0a0' @@ -4415,7 +4587,7 @@ package: - category: main dependencies: cairo: '>=1.16.0,<2.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' fribidi: '>=1.0.10,<2.0a0' @@ -4424,14 +4596,14 @@ package: libglib: '>=2.74.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' hash: - md5: 667dc93c913f0156e1237032e3a22046 - sha256: 7ae10db69ed593d8e51205dfc8a8297b09bfc9aa351f0e07199d4edccb16ca13 + md5: a8b9e35dd7be2c945b0de4fe19a7c3a9 + sha256: 80648fb4691839a81f83fe55f4353357d198cd75e61dbb61b815e39d577e87d2 manager: conda name: pango optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.12-hd33c08f_1.conda - version: 1.50.12 + url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-hd33c08f_0.conda + version: 1.50.14 - category: main dependencies: bcrypt: '>=3.2' @@ -4439,14 +4611,14 @@ package: pynacl: '>=1.5' python: '>=3.6' hash: - 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version: 1.2.1 + url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz + version: 1.2.2 version: 1 diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 17e6c2dd..ca4c96d2 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -9,26 +9,24 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-circt/conda-reqs/riscv-tools.yaml -f /scratch/abejgonza/chipyard/conda-reqs/chipyard.yaml -f /scratch/abejgonza/chipyard/conda-reqs/riscv-tools.yaml -f /Users/joonhohwangbo/Documents/Research/coding/chipyard/conda-reqs/chipyard.yaml -f /Users/joonhohwangbo/Documents/Research/coding/chipyard/conda-reqs/riscv-tools.yaml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - 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version: 3.0.8 + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-h0b41bf4_0.conda + version: 3.1.0 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -1053,15 +1050,15 @@ package: version: 0.11.1 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 1e15f6ad85a7d743a2ac68dae6c82b98 - sha256: d45c4d1c8372c546711eb3863c76d899d03a67c3edb3b5c2c46c9492814cbe03 + md5: bce9f945da8ad2ae9b1d7165a64d0f87 + sha256: b8dda3b560e8a7830fe23be1c58cc41f407b2e20ae2f3b6901eb5842ba62b743 manager: conda name: xorg-xextproto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-xextproto-7.3.0-h7f98852_1002.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-xextproto-7.3.0-h0b41bf4_1003.conda version: 7.3.0 - category: main dependencies: @@ -1222,6 +1219,32 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-16_linux64_openblas.tar.bz2 version: 3.9.0 +- category: main + dependencies: + libbrotlicommon: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: 4ae4d7795d33e02bd20f6b23d91caf82 + sha256: d88ba07c3be27c89cb4975cc7edf63ee7b1c62d01f70d5c3f7efeb987c82b052 + manager: conda + name: libbrotlidec + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlidec-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 +- category: main + dependencies: + libbrotlicommon: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: 04bac51ba35ea023dc48af73c1c88c25 + sha256: a0468858b2f647f51509a32040e93512818a8f9980f20b3554cccac747bcc4be + manager: conda + name: libbrotlienc + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlienc-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1269,16 +1292,16 @@ package: libgcc-ng: '>=12' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' - openssl: '>=3.0.7,<4.0a0' + openssl: '>=3.0.8,<4.0a0' hash: - md5: dd682f0b6d65e75b2bc868fc8e93d87e - sha256: acb80dfd0b7be38c47101df812fc903374c8408daec127edb6f11a648a67c243 + md5: 613955a50485812985c059e7b269f42e + sha256: ecd6b08c2b5abe7d1586428c4dd257dcfa00ee53700d79cdc8bca098fdfbd79a manager: conda name: libnghttp2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libnghttp2-1.51.0-hff17c54_0.conda - version: 1.51.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libnghttp2-1.52.0-h61bc06f_0.conda + version: 1.52.0 - category: main dependencies: libgcc-ng: '>=12' @@ -1356,13 +1379,13 @@ package: libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: 3b933ea47ef8f330c4c068af25fcd6a8 - sha256: b30713fb4477ff4f722280d956593e7e7a2cb705b7444dcc278de447432b43b1 + md5: bb808b654bdc3c783deaf107a2ffb503 + sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-h7463322_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda version: 2.10.3 - category: main dependencies: @@ -1380,16 +1403,16 @@ package: - category: main dependencies: gmp: '>=6.2.1,<7.0a0' - libgcc-ng: '>=7.5.0' + libgcc-ng: '>=12' hash: - md5: ea9ebeddb066da8fad4a815e61b139be - sha256: d2d71ac6ed3b32f06b7db2691e0a1760016ce13fb0c50a9de6ed1ccc33e35ff3 + md5: 14d87bdff2cbd3b1179a29fb316ed743 + sha256: 03097f21c75b0936471809e533dbae44af9d9ae696ecf264d1a929fc9f9e4b83 manager: conda name: mpfr optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.1.0-h9202a9a_1.tar.bz2 - version: 4.1.0 + url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.2.0-hb012696_0.conda + version: 4.2.0 - category: main dependencies: libffi: '>=3.4.2,<3.5.0a0' @@ -1591,6 +1614,20 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/bison-3.8-h9c3ff4c_0.tar.bz2 version: '3.8' +- category: main + dependencies: + libbrotlidec: 1.0.9 h166bdaf_8 + libbrotlienc: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: e5613f2bc717e9945840ff474419b8e4 + sha256: ab1994e03bdd88e4b27f9f802ac18e45ed29b92cce25e1fd86da43b89734950f + manager: conda + name: brotli-bin + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/brotli-bin-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: gcc_impl_linux-64: '>=12.2.0,<12.2.1.0a0' @@ -1773,13 +1810,13 @@ package: libzlib: '>=1.2.13,<1.3.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 70cbb0c2033665f2a7339bf0ec51a67f - sha256: 3fb9a9cfd2f5c79e8116c67f95d5a9b790ec66807ae0d8cebefc26fda9f836a7 + md5: 17d91085ccf5934ce652cb448d0cb65a + sha256: f649fac60cb122bf0d85c4955725d94c353fdbd768bcd44f0444979b363cc9ab manager: conda name: libllvm15 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm15-15.0.7-hadd5161_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libllvm15-15.0.7-hadd5161_1.conda version: 15.0.7 - category: main dependencies: @@ -1850,14 +1887,14 @@ package: tzdata: '' xz: '>=5.2.6,<6.0a0' hash: - md5: 95c9b7c96a7fd7342e0c9d0a917b8f78 - sha256: 00bcb28a294aa78bf9d2a2ecaae8cb887188eae710f9197d823d36fb8a5d9767 + md5: 3cb3e91b3fe66baa68a12c85f39b9b40 + sha256: 073878d7cc9c7e25cf04983d02e6d44b531d47e0166258cbce964dd78bb716a9 manager: conda name: python optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/python-3.9.16-h2782a2a_0_cpython.conda - version: 3.9.16 + url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.9-he550d4f_0_cpython.conda + version: 3.10.9 - category: main dependencies: libgcc-ng: '>=12' @@ -1911,19 +1948,20 @@ package: version: 1.20.3 - category: main dependencies: - libgcc-ng: '>=9.3.0' - libxcb: 1.* + libgcc-ng: '>=12' + libxcb: '>=1.13,<1.14.0a0' xorg-kbproto: '' + xorg-xextproto: '>=7.3.0,<8.0a0' xorg-xproto: '' hash: - md5: 12a61e640b8894504326aadafccbb790 - sha256: ec4641131e3afcb4b34614a5fa298efb34f54c2b2960bf9a73a8d202140d47c4 + md5: ea8fbfeb976ac49cbeb594e985393514 + sha256: 3c6862a01a39cdea3870b132706ad7256824299947a3a94ae361d863d402d704 manager: conda name: xorg-libx11 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libx11-1.7.2-h7f98852_0.tar.bz2 - version: 1.7.2 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libx11-1.8.4-h0b41bf4_0.conda + version: 1.8.4 - category: main dependencies: python: '>=3.6' @@ -1952,14 +1990,14 @@ package: dependencies: python: '>=3.6' hash: - md5: f3f2ab3ce28979a24d1a988ba211eb9b - sha256: 1354731d0eb1b406b66b3cb3d6ab74d7cbe9c0ec1d30b9e5afa366d4539e4687 + md5: b3c15cb1d45fd10bc6f652bbc51e023a + sha256: 8dbc6de55113ea67a64f0be5d16ba939d1b58a25dbd9a5cc62b571cef24ef85c manager: conda - name: asn1crypto + name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/asn1crypto-1.5.1-pyhd8ed1ab_0.tar.bz2 - version: 1.5.1 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda + version: 3.0.2 - category: main dependencies: libgcc-ng: '>=12' @@ -1986,6 +2024,21 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/attrs-22.2.0-pyh71513ae_0.conda version: 22.2.0 +- category: main + dependencies: + brotli-bin: 1.0.9 h166bdaf_8 + libbrotlidec: 1.0.9 h166bdaf_8 + libbrotlienc: 1.0.9 h166bdaf_8 + libgcc-ng: '>=12' + hash: + md5: 2ff08978892a3e8b954397c461f18418 + sha256: 74c0fa22ea7c62d2c8f7a7aea03a3bd4919f7f3940ef5b027ce0dfb5feb38c06 + manager: conda + name: brotli + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/brotli-1.0.9-h166bdaf_8.tar.bz2 + version: 1.0.9 - category: main dependencies: python: '>=3.6' @@ -2063,26 +2116,26 @@ package: dependencies: python: '' hash: - md5: 9cf68a6826504feedbfd646bc4d1ca14 - sha256: c04c09570a8bccf45bb73ae63d7e396d66c01580f9125ce5e5c981a2be549a51 + md5: c08b4c1326b880ed44f3ffb04803332f + sha256: ddf1749f0fd5a098a7954d98267cebca83a36b86719ce4ab6fc4aa94ef518432 manager: conda name: colorama optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/colorama-0.4.3-py_0.tar.bz2 - version: 0.4.3 + url: https://conda.anaconda.org/conda-forge/noarch/colorama-0.4.4-pyh9f0ad1d_0.tar.bz2 + version: 0.4.4 - category: main dependencies: python: '>=3.6,<4.0' hash: - md5: b8477552274c1cfdb533e954c76523f1 - sha256: af1db267e03c649aefcc1571ddce4eac361a0e5232d1bdd05fd93fadbfdd2da6 + md5: 709a2295dd907bb34afb57d54320642f + sha256: 2f05954a3faf0700c14c1deddc085385160ee32abe111699c78d9cb277e915cc manager: conda name: crashtest optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/crashtest-0.3.1-pyhd8ed1ab_0.tar.bz2 - version: 0.3.1 + url: https://conda.anaconda.org/conda-forge/noarch/crashtest-0.4.1-pyhd8ed1ab_0.tar.bz2 + version: 0.4.1 - category: main dependencies: python: '>=3.6' @@ -2123,29 +2176,41 @@ package: version: 0.3.6 - category: main dependencies: - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: eeb35a5548c9b90fcfd6b36bc013557b - sha256: b9cfde2a6a78a54f3e8e65f009cf9d6faabface5e96d66d65d278be7c577f0e5 + md5: 9815d5a3a63926f0877313c07b7c5d90 + sha256: ccf4e2d33f1e2c376de05d0ca93e0cc3fccac9785c5a832e6fca9cc1ce3f7470 manager: conda name: docutils optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/docutils-0.15.2-py39hf3d152e_6.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/docutils-0.15.2-py310hff52083_6.tar.bz2 version: 0.15.2 - category: main dependencies: python: '>=3.7' hash: - md5: 1addc115923d646ca19ed90edc413506 - sha256: 739c48f62747c942aa733041d36a2c1af41c2ecf2a59f1fec90cd7200e01be9a + md5: 7312299d7a0ea4993159229b7d2dceb2 + sha256: f073c3ba993912f1c0027bc34a54975642885f0a4cd5f9dc42a17ca945df2c18 + manager: conda + name: exceptiongroup + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/exceptiongroup-1.1.1-pyhd8ed1ab_0.conda + version: 1.1.1 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 6f90f1dc834447823b11d155726fcb37 + sha256: 6a6901f20c5b4d81aebd25a0645b3578ebb6a323f9fd7e87ee05ecbcfe19069e manager: conda name: filelock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.9.0-pyhd8ed1ab_0.conda - version: 3.9.0 + url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.10.0-pyhd8ed1ab_0.conda + version: 3.10.0 - category: main dependencies: expat: '>=2.5.0,<3.0a0' @@ -2162,6 +2227,32 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/fontconfig-2.14.2-h14ed4e7_0.conda version: 2.14.2 +- category: main + dependencies: + libgcc-ng: '>=12' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 + hash: + md5: 25e1626333f9a0646579a162e7b174ee + sha256: 1a213bfa274e847d08cf0d8b068dc94be002c9f17acd040b5c9f2ead80c3c7c0 + manager: conda + name: frozenlist + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/frozenlist-1.3.3-py310h5764c6d_0.tar.bz2 + version: 1.3.3 +- category: main + dependencies: + python: '>=3.8' + hash: + md5: 0db48a2f5a68e28e5af8d3df276f2255 + sha256: dfcee90620d13f4f667664620191d780c79ec7e9ba9908cd771d24a1361e0cc9 + manager: conda + name: fsspec + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.3.0-pyhd8ed1ab_1.conda + version: 2023.3.0 - category: main dependencies: jpeg: '>=9e,<10a' @@ -2184,16 +2275,16 @@ package: libgcc-ng: '>=12' mpc: '>=1.2.1,<2.0a0' mpfr: '>=4.1.0,<5.0a0' - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: d019ebf9a328e19c211be7e916c57b80 - sha256: f5a5ab463d7d9e9c4f6a70748adf334ad28072c9befe4748d0eaa48fccc24d56 + md5: 73f6fa50c32ddd985cf5fba7b890a75c + sha256: aeb52e14f33c17e11248bfe58383b935e101d86e89b5246373c590c7b127ab47 manager: conda name: gmpy2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gmpy2-2.1.2-py39h376b7d2_1.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gmpy2-2.1.2-py310h3ec546c_1.tar.bz2 version: 2.1.2 - category: main dependencies: @@ -2224,16 +2315,16 @@ package: version: 12.2.0 - category: main dependencies: - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: 3844897723d78cca5f813ad6bee5fc7b - sha256: e15ee3e17a30738fb8e2adccef809a41b388bcaf3cc9fc895c15287a86e93ce1 + md5: 43bd27c73e9e3b0bc508217ae409798f + sha256: dab441ddc4592e34b490fed4235c2c0b10b54616509c7ebc176c37c8389600d6 manager: conda name: humanfriendly optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/humanfriendly-10.0-py39hf3d152e_4.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/humanfriendly-10.0-py310hff52083_4.tar.bz2 version: '10.0' - category: main dependencies: @@ -2297,16 +2388,16 @@ package: version: 0.8.0 - category: main dependencies: - python: '' + python: '>=3.7' hash: - md5: 5988f73e79824c7900954539fbfad3fa - sha256: f75db900a1886fc0813af806a127186506c669431b73a92600de06aadae922ae + md5: 2cfa3e1cf3fb51bb9b17acc5b5e9ea11 + sha256: 95ac5f9ee95fd4e34dc051746fc86016d3d4f6abefed113e2ede049d59ec2991 manager: conda name: jmespath optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/jmespath-0.10.0-pyh9f0ad1d_0.tar.bz2 - version: 0.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/jmespath-1.0.1-pyhd8ed1ab_0.tar.bz2 + version: 1.0.1 - category: main dependencies: python: '>=3.6' @@ -2333,33 +2424,33 @@ package: version: '2.0' - category: main dependencies: - libgcc-ng: '>=9.3.0' - libstdcxx-ng: '>=9.3.0' - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: c5d6241b3ec5d02c316a5f66f14024c7 - sha256: 32fa01aacf67d40b54fbcf9c7e89aae964450ffdb58bb93baba068d8b5c72c3e + md5: ad5647e517ba68e2868ef2e6e6ff7723 + sha256: f56d1772472b90ddda6fd0963a80dcf1960f1277b9653667a9bde62ae125f972 manager: conda name: kiwisolver optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/kiwisolver-1.3.1-py39h1a9c180_1.tar.bz2 - version: 1.3.1 + url: https://conda.anaconda.org/conda-forge/linux-64/kiwisolver-1.4.4-py310hbf28c38_1.tar.bz2 + version: 1.4.4 - category: main dependencies: jpeg: '>=9e,<10a' libgcc-ng: '>=12' libtiff: '>=4.5.0,<4.6.0a0' hash: - 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category: main dependencies: clang-format: 15.0.7 default_had23c3d_1 @@ -4349,14 +4482,14 @@ package: python: '>=3.6' ukkonen: '' hash: - md5: e07a5691c27e65d8d3d9278c578c7771 - sha256: 922faccc66c0855cb6ed44e68739283842e9a2f4836ece192cb2f971ad057935 + md5: b5ada314668cded097e08fea86262317 + sha256: 88bcba64d462867b5759e29784cf24685e1e49fffea75452b94d438d6bd9587c manager: conda name: identify optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.18-pyhd8ed1ab_0.conda - version: 2.5.18 + url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.21-pyhd8ed1ab_0.conda + version: 2.5.21 - category: main dependencies: importlib_metadata: '' @@ -4384,6 +4517,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/libdwarf-dev-0.0.0.20190110_28_ga81397fc4-h753d276_0.tar.bz2 version: 0.0.0.20190110_28_ga81397fc4 +- category: main + dependencies: + jsonschema: '>=3.0.0,<5.0.0' + python: '>=3.7' + hash: + md5: 277aff70bb1def188c9c016ba4564e23 + sha256: 0c2f971f86211f2b6db431de9d8ab4c9e38eed5422bd06f93cd8be3cbb882a2c + manager: conda + name: openapi-schema-validator + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/openapi-schema-validator-0.2.3-pyhd8ed1ab_0.tar.bz2 + version: 0.2.3 - category: main dependencies: alsa-lib: '>=1.2.8,<1.2.9.0a0' @@ -4416,7 +4562,7 @@ package: - category: main dependencies: cairo: '>=1.16.0,<2.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' fribidi: '>=1.0.10,<2.0a0' @@ -4425,14 +4571,14 @@ package: libglib: '>=2.74.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' hash: - md5: 667dc93c913f0156e1237032e3a22046 - sha256: 7ae10db69ed593d8e51205dfc8a8297b09bfc9aa351f0e07199d4edccb16ca13 + md5: a8b9e35dd7be2c945b0de4fe19a7c3a9 + sha256: 80648fb4691839a81f83fe55f4353357d198cd75e61dbb61b815e39d577e87d2 manager: conda name: pango optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.12-hd33c08f_1.conda - version: 1.50.12 + url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-hd33c08f_0.conda + version: 1.50.14 - category: main dependencies: bcrypt: '>=3.2' @@ -4440,14 +4586,14 @@ package: pynacl: '>=1.5' python: '>=3.6' hash: - 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litex-hub - nodefaults platforms: @@ -14,4 +15,4 @@ dependencies: # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications # documentation on package_spec syntax for constraining versions - - riscv-tools=1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock + - riscv-tools=1.0.3 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst index 4a467207..1113bde6 100644 --- a/docs/Customization/Firrtl-Transforms.rst +++ b/docs/Customization/Firrtl-Transforms.rst @@ -10,15 +10,18 @@ Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chi The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler ------------------------------------------------------ -In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler(SFC) and the MLIR FIRRTL compiler(MFC). -They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster. In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will -compile CHIRRTL into Verilog(as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied. +In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC). +They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will +compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, +we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied. + +For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/. Where to add transforms ----------------------- -In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Harness" file containing the test harness, which instantiates the DUT. -The "Harness" file does not contain the DUT's module definition or any of its submodules. +In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Model" file containing the test harness, which instantiates the DUT. +The "Model" file does not contain the DUT's module definition or any of its submodules. This is done by the ``tapeout`` SBT project (located in ``tools/barstools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms). .. literalinclude:: ../../common.mk diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index c92ad201..364f31cb 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -75,3 +75,9 @@ We can use this config fragment when composing our configs. .. note:: Readers who want more information on the configuration system may be interested in reading :ref:`cdes`. + +Chipyard Config Fragments +------------------------- + +For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments +(config. fragments that match "class NAME extends CONFIG\n" on a single line and a subset of their children) and their file path in a fully initialized Chipyard repository. diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index 204eacec..15347cf8 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -1,8 +1,62 @@ Running a Design on Arty ======================== -Basic Arty Design ------------------ +Arty100T Instructions +---------------------- + +The default Xilinx Arty 100T harness uses a TSI-over-UART adapter to bringup the FPGA. +A user can connect to the Arty 100T target using a special ``uart_tsi`` program that opens a UART TTY. +The interface for the ``uart_tsi`` program provides unique functionality that is useful for bringing up test chips. + +To build the design, run: + +.. code-block:: shell + + cd fpga/ + make SUB_PROJECT=arty100t + +To build the UART-based frontend server, run: + +.. code-block:: shell + + cd generators/testchipip/uart_tsi + make + +After programming the bitstream, and connecting the Arty's UART to a host PC via the USB cable, the ``uart_tsi`` program can be run to interact with the target. + +Running a program: + +.. code-block:: shell + + ./uart_tsi +tty=/dev/ttyUSBX dhrystone.riscv + +Probe an address on the target system: + +.. code-block:: shell + + ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none + +Write some address before running a program: + +.. code-block:: shell + + ./uart_tsi +tty=/dev/ttyUSBX +init_write=0x80000000:0xdeadbeef none + +Self-check that binary loading proceeded correctly: + +.. code-block:: shell + + ./uart_tsi +tty=/dev/ttyUSBX +selfcheck dhrystone.riscv + +Run a design at a higher baud rate than default (For example, if ``CONFIG=UART921600RocketArty100TConfig`` were built): + +.. code-block:: shell + + ./uart_tsi +tty=/dev/ttyUSBX +baudrate=921600 dhrystone.riscv + + +Arty35T Legacy Instructions +--------------------------- The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__. The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC. diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 5fd3ee75..d62f6f1c 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -188,6 +188,16 @@ An open-source vcd-capable waveform viewer is `GTKWave `__. + +The ``*.graphml`` file will be located in ``generated-src/<...>/``. Open the file in the graph viewer. +To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings. + .. _sw-sim-verilator-opts: Additional Verilator Options diff --git a/docs/Tools/Chisel-Testers.rst b/docs/Tools/Chisel-Testers.rst deleted file mode 100644 index 9570dd61..00000000 --- a/docs/Tools/Chisel-Testers.rst +++ /dev/null @@ -1,7 +0,0 @@ -Chisel Testers -============================== - -`Chisel Testers `__ is a library for writing tests for Chisel designs. -It provides a Scala API for interacting with a DUT. -It can use multiple backends, including things such as Treadle and Verilator. -See :ref:`Tools/Treadle:Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods. diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst index e9e6425a..2e88218f 100644 --- a/docs/Tools/FIRRTL.rst +++ b/docs/Tools/FIRRTL.rst @@ -3,8 +3,10 @@ FIRRTL `FIRRTL `__ is an intermediate representation of your circuit. It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog. -Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations. +Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which passes the circuit through a series of circuit-level transformations. An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. Once the transformations are done, a Verilog file is emitted and the build process is done. -For more information on please visit their `website `__. +To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section. + +For more information on FIRRTL, please visit their `website `__. diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index fecb2043..88161269 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -11,7 +11,6 @@ The following pages will introduce them, and how we can use them in order to gen Chisel FIRRTL Treadle - Chisel-Testers Dsptools Barstools Dromajo diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index ddeda299..2da52d24 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -2,7 +2,7 @@ ASAP7 Tutorial ============== -The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. +The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Mentor tool plugin submodule, which is needed for DRC & LVS. Project Structure ----------------- @@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc CONFIG=TinyRocketConfig - ./build/drc-rundir/generated-scripts/view-drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc make lvs CONFIG=TinyRocketConfig - ./build/lvs-rundir/generated-scripts/view-lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 10c2a9ec..cc200c44 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -162,7 +162,7 @@ Simulation-exacted power estimation often requires a dedicated testharness for t The simulation-extracted power estimation flow implicitly uses Hammer's gate-level simulation flow (in order to generate the ``saif`` activity data file). This gate-level simulation flow can also be run independantly from the power estimation flow using the ``make sim-par`` command. -.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Incisive is work-in-progress) +.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Xcelium is work-in-progress) Signoff diff --git a/docs/VLSI/Hammer.rst b/docs/VLSI/Hammer.rst index b36f6e06..d4f787ca 100644 --- a/docs/VLSI/Hammer.rst +++ b/docs/VLSI/Hammer.rst @@ -46,7 +46,7 @@ The current set of all available Hammer APIs is codified `here `__ +* Sky130A PDK, install `using conda `__ or `these directions `__ +* `Sram22 Sky130 SRAM macros `__ + + * These SRAM macros were generated using the `Sram22 SRAM generator `__ (still very heavily under development) + +Quick Prerequisite Setup +^^^^^^^^^^^^^^^^^^^^^^^^ +As of recently, the Sky130A PDK may be installed via conda. +The prerequisite setup for this tutorial may eventually be scripted, but for now the directions to set them up are below. + +.. code-block:: shell + + # download all files for Sky130A PDK + conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9 + # clone the SRAM22 Sky130 SRAM macros + git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros + Initial Setup ------------- @@ -59,6 +75,38 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. +Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory. +We will summarize a few files in this directory that will be important for the rest of the tutorial. + +.. code-block:: shell + + cd ~chipyard/vlsi + +example-vlsi-sky130 +^^^^^^^^^^^^^^^^^^^ +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. + + +example-sky130.yml +^^^^^^^^^^^^^^^^^^ +This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. + +Add the following YAML keys to the top of this file to specify the location of the Sky130A PDK and SRAM macros. + +.. code-block:: yaml + + # all ~ should be replaced with absolute paths to these directories + # technology paths + technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A + technology.sky130.sram22_sky130_macros: ~/sram22_sky130_macros + + +example-tools.yml +^^^^^^^^^^^^^^^^^ +This contains the Hammer configuration for a commercial tool flow. +It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre). + + Building the Design -------------------- To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow: @@ -71,12 +119,21 @@ The command ``make buildfile`` generates a set of Make targets in ``build/hammer It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. +The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources +and (2) the mapping of memory instances in the design to SRAM macros; +all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +Note that the files in ``generated-src`` vary for each tool/technology flow. +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows +(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate +chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. + + For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-commercial``, which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows: * ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. * ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin -* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described below +* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described above * ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` * ``VLSI_OBJ_DIR=build-sky130-commercial`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity. * ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs. @@ -84,24 +141,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi Running the VLSI Flow --------------------- -example-vlsi-sky130 -^^^^^^^^^^^^^^^^^^^ -This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. - - -example-sky130.yml -^^^^^^^^^^^^^^^^^^ -This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. - -First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the -`Sky130 Hammer plugin README `__ -for details about the PDK setup. - -example-tools.yml -^^^^^^^^^^^^^^^^^ -This contains the Hammer configuration for a commercial tool flow. -It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre). - Synthesis ^^^^^^^^^ .. code-block:: shell @@ -160,3 +199,20 @@ Post-P&R power and rail (IR drop) analysis is supported with Voltus: If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim--debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform. To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported. + + +VLSI Flow Control +^^^^^^^^^^^^^^^^^ +Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action. + +.. code-block:: shell + + # the following two statements are equivalent because the + # extraction step immediately precedes the write_design step + make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction" + make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design" + + # example of re-running only floorplanning to test out a new floorplan configuration + # the "-p file.yml" causes file.yml to override any previous yaml/json configurations + make redo-par \ + HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-designs/sky130-openroad.yml" diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 4518e853..882429d7 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * ``env.yml`` - * A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here `__. + * This file is not used in this tutorial, but is required for the commercial tool flow. A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here `__. * ``example-vlsi-sky130`` @@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * ``example-sky130.yml``, ``example-openroad.yml``, ``example-designs/sky130-openroad.yml`` - * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here `__. + * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example Sky130 config is found `here `__. * ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml`` @@ -48,12 +48,35 @@ Prerequisites * Python 3.9+ * OpenROAD flow tools: - * Yosys (synthesis), install `from source `__ or `using conda `__ - * OpenROAD (place-and-route), install `from source `__ - * Magic (DRC), install `from source `__ - * NetGen (LVS), install `from source `__ or `using conda `__ + * Yosys (synthesis), install `using conda `__ or `from source `__ + * OpenROAD (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or `from source `__ + * KLayout (DEF to GDSII conversion), install `using conda `__ or `from source `__ + * Magic (DRC), , install `using conda `__ or `from source `__ + * NetGen (LVS), , install `using conda `__ or `from source `__ -* Sky130 PDK, install using `these directions `__ +* Sky130A PDK, install `using conda `__ or `these directions `__ +* `Sram22 Sky130 SRAM macros `__ + + * These SRAM macros were generated using the `Sram22 SRAM generator `__ (still very heavily under development) + +Quick Prerequisite Setup +^^^^^^^^^^^^^^^^^^^^^^^^ +As of recently, most of the prerequisites of this tutorial may now be installed as conda packages. +The prerequisite setup for this tutorial may eventually be scripted, but for now the directions to set them up are below. +Note that we create a new conda environment for each tool because some of them have conflicting dependencies. + +.. code-block:: shell + + # download all files for Sky130A PDK + conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9 + # clone the SRAM22 Sky130 SRAM macros + git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros + + # install all VLSI tools + conda create -c litex-hub --prefix ~/.conda-yosys yosys=0.27_4_gb58664d44 + conda create -c litex-hub --prefix ~/.conda-openroad openroad=2.0_7070_g0264023b6 + conda create -c litex-hub --prefix ~/.conda-klayout klayout=0.28.5_98_g87e2def28 + conda create -c litex-hub --prefix ~/.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172 Initial Setup ------------- @@ -66,31 +89,13 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder, and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder. -Building the Design --------------------- -To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow: +Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory. +We will summarize a few files in this directory that will be important for the rest of the tutorial. .. code-block:: shell - make buildfile tutorial=sky130-openroad + cd ~chipyard/vlsi -The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. -It needs to be re-run if environment variables are changed. -It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. - -For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``, -which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows: - -* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. -* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin -* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below -* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` -* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity. -* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs. -* ``ENABLE_CUSTOM_FIRRTL_PASS = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog. - -Running the VLSI Flow ---------------------- example-vlsi-sky130 ^^^^^^^^^^^^^^^^^^^ @@ -101,16 +106,70 @@ example-sky130.yml ^^^^^^^^^^^^^^^^^^ This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. -First, set ``technology.sky130.`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the -`Sky130 Hammer plugin README `__ -for details about the PDK setup. +Add the following YAML keys to the top of this file to specify the location of the Sky130A PDK and SRAM macros. +.. code-block:: yaml + + # all ~ should be replaced with absolute paths to these directories + # technology paths + technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A + technology.sky130.sram22_sky130_macros: ~/sram22_sky130_macros example-openroad.yml ^^^^^^^^^^^^^^^^^^^^ This contains the Hammer configuration for the OpenROAD tool flow. It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen). +Add the following YAML keys to the top of this file to specify the locations of the tool binaries. +Note that this is not required if the tools are already on your PATH. + +.. code-block:: yaml + + # all ~ should be replaced with absolute paths to these directories + # tool binary paths + synthesis.yosys.yosys_bin: ~/.conda-yosys/bin/yosys + par.openroad.openroad_bin: ~/.conda-openroad/bin/openroad + par.openroad.klayout_bin: ~/.conda-klayout/bin/klayout + drc.magic.magic_bin: ~/.conda-signoff/bin/magic + lvs.netgen.netgen_bin: ~/.conda-signoff/bin/netgen + + +Building the Design +-------------------- + +To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow: + +.. code-block:: shell + + make buildfile tutorial=sky130-openroad + +The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. +It needs to be re-run if environment variables are changed. +It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. + +The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources +and (2) the mapping of memory instances in the design to SRAM macros; +all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +Note that the files in ``generated-src`` vary for each tool/technology flow. +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows +(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate +chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. + + +For the sake of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``, +which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows: + +* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. +* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin +* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described above +* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` +* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity. +* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs. +* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog. + +Running the VLSI Flow +--------------------- + Synthesis ^^^^^^^^^ @@ -128,38 +187,79 @@ Place-and-Route make par tutorial=sky130-openroad +Note that sometimes OpenROAD freezes on commands following the ``detailed_route`` step, +so for now we recomment running place-and-route until the ``extraction`` step, +then re-starting the flow at this step. See the :ref:`VLSI/Sky130-OpenROAD-Tutorial:VLSI Flow Control` documentation +below for how to break up the flow into these steps. + After completion, the final database can be opened in an interactive OpenROAD session. +Hammer generates a convenient script to launch these sessions .. code-block:: shell - cd ./build/par-rundir + cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated-scripts/open_chip +Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout, +you will need to install OpenROAD from source. Below is the post-PnR layout for the TinyRocketConfig in Sky130 generated by OpenROAD. .. image:: ../_static/images/vlsi-openroad-par-tinyrocketconfig.png -Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action. These databases can be restored in an interactive OpenROAD session as desired for debugging purposes. +Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action, +These databases can be restored using the same ``open_chip`` script for debugging purposes. .. code-block:: shell - openroad # launch OpenROAD tool - openroad> read_db pre_global_route + cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + ./generated_scripts/open_chip -h + " + Usage: ./generated-scripts/open_chip [-t] [openroad_db_name] -.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. + Options + openroad_db_name : Name of database to load (default=latest) + -t, --timing : Load timing info (default=disabled because of slow load time) + -h, --help : Display this message + " + # load pre-global route database without timing information + ./generated_scripts/open_chip pre_global_route + + # load post-clock tree database with timing inforamtion + ./generated_scripts/open_chip -t post_clock_tree + +Various reports, including timing reports, are found in ``build/par-rundir/reports``. + +See the `OpenROAD tool plugin `__ for the full list of OpenROAD tool steps and their implementations. DRC & LVS ^^^^^^^^^ -To run DRC & LVS: + +As a note, this tutorial has been run extensively through commercial signoff tools, +thus the open-source signoff flow is not stable or guaranteed to produce useful results. +We welcome any contributions to improving both our `Magic tool plugin `__ +and `Netgen tool plugin `__. + +To run DRC & LVS in Magic & Netgen, respectively: .. code-block:: shell make drc tutorial=sky130-openroad + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-openroad + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs -Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the -`Sky130 Hammer plugin README `__. +Note that in ``sky130-openroad.yml`` we have set the following YAML keys: + +.. code-block:: yaml + + drc.magic.generate_only: true + lvs.netgen.generate_only: true + +These keys cause the Hammer plugin to only generate all necessary scripts, without executing them with the respective tool. +This is because Magic and Netgen, as of the writing of this tutorial, do not have a database format that may be loaded interactively, +so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks, +which is done by the ``generated-scripts/view_[drc|lvs]`` scripts. VLSI Flow Control @@ -168,15 +268,20 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below .. code-block:: shell - # the following two statements are equivalent because the - # extraction step immediately precedes the write_design step + # the following two commands run the entire flow, using the pre_extraction + # database to save and reload a checkpoint of the design + make par HAMMER_EXTRA_ARGS="--stop_after_step extraction" + make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction" + + # the following two commands are equivalent because the extraction + # step immediately precedes the write_design step make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction" make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design" # example of re-running only floorplanning to test out a new floorplan configuration - make redo-par HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-sky130.yml" - -See the `OpenROAD tool plugin `__ for the full list of OpenROAD tool steps and their implementations. + # the "-p file.yml" causes file.yml to override any previous yaml/json configurations + make redo-par \ + HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-designs/sky130-openroad.yml" Documentation ------------- diff --git a/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png b/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png index 0d8ce137..2f399e2b 100644 Binary files a/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png and b/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png differ diff --git a/fpga/Makefile b/fpga/Makefile index e02dac54..7521b1ed 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -57,7 +57,6 @@ ifeq ($(SUB_PROJECT),bringup) BOARD ?= vcu118 FPGA_BRAND ?= xilinx endif - ifeq ($(SUB_PROJECT),arty) # TODO: Fix with Arty SBT_PROJECT ?= fpga_platforms @@ -72,6 +71,20 @@ ifeq ($(SUB_PROJECT),arty) BOARD ?= arty FPGA_BRAND ?= xilinx endif +ifeq ($(SUB_PROJECT),arty100t) + # TODO: Fix with Arty + SBT_PROJECT ?= fpga_platforms + MODEL ?= Arty100THarness + VLOG_MODEL ?= Arty100THarness + MODEL_PACKAGE ?= chipyard.fpga.arty100t + CONFIG ?= RocketArty100TConfig + CONFIG_PACKAGE ?= chipyard.fpga.arty100t + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= arty_a7_100 + FPGA_BRAND ?= xilinx +endif include $(base_dir)/variables.mk @@ -109,8 +122,7 @@ include $(base_dir)/common.mk # copy from other directory ######################################################################################### all_vsrcs := \ - $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ - $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v + $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v ######################################################################################### # vivado rules diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 474ad191..b6cd1bb7 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 474ad19113b89ed5679695b269acdb011b9b871a +Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9 diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 1c81f481..a88848d0 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -15,30 +15,20 @@ import testchipip.{SerialTLKey} import chipyard.{BuildSystem} -class WithDefaultPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => List( - UARTParams(address = 0x10013000)) - case DTSTimebase => BigInt(32768) - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = 2, - idcodePartNum = 0x000, - idcodeManufId = 0x489, - debugIdleCycles = 5) - case SerialTLKey => None // remove serialized tl port -}) - // DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ new WithDebugResetPassthrough ++ - new WithDefaultPeripherals ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2) + + new chipyard.config.WithDTSTimebase(32768) ++ + new testchipip.WithNoSerialTL ) class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ + new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ new chipyard.TinyRocketConfig ) // DOC include end: AbstractArty and Rocket diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala new file mode 100644 index 00000000..0930dbdb --- /dev/null +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -0,0 +1,59 @@ +// See LICENSE for license details. +package chipyard.fpga.arty100t + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.system._ +import freechips.rocketchip.tile._ + +import sifive.blocks.devices.uart._ +import sifive.fpgashells.shell.{DesignKey} + +import testchipip.{SerialTLKey} + +import chipyard.{BuildSystem} + +// don't use FPGAShell's DesignKey +class WithNoDesignKey extends Config((site, here, up) => { + case DesignKey => (p: Parameters) => new SimpleLazyModule()(p) +}) + +class WithArty100TTweaks extends Config( + new WithArty100TUARTTSI ++ + new WithArty100TDDRTL ++ + new WithNoDesignKey ++ + new chipyard.config.WithNoDebug ++ // no jtag + new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad + new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us + new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY + new freechips.rocketchip.subsystem.WithoutTLMonitors) + +class RocketArty100TConfig extends Config( + new WithArty100TTweaks ++ + new chipyard.config.WithMemoryBusFrequency(50.0) ++ + new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithBroadcastManager ++ // no l2 + new chipyard.RocketConfig) + +class UART230400RocketArty100TConfig extends Config( + new WithArty100TUARTTSI(uartBaudRate = 230400) ++ + new RocketArty100TConfig) + +class UART460800RocketArty100TConfig extends Config( + new WithArty100TUARTTSI(uartBaudRate = 460800) ++ + new RocketArty100TConfig) + +class UART921600RocketArty100TConfig extends Config( + new WithArty100TUARTTSI(uartBaudRate = 921600) ++ + new RocketArty100TConfig) + + +class NoCoresArty100TConfig extends Config( + new WithArty100TTweaks ++ + new chipyard.config.WithMemoryBusFrequency(50.0) ++ + new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency + new chipyard.config.WithBroadcastManager ++ // no l2 + new chipyard.NoCoresConfig) diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala new file mode 100644 index 00000000..5cc1e348 --- /dev/null +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -0,0 +1,92 @@ +package chipyard.fpga.arty100t + +import chisel3._ +import chisel3.util._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset} + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} +import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} + +import sifive.blocks.devices.uart._ + +import chipyard._ +import chipyard.harness.{ApplyHarnessBinders} +import chipyard.iobinders.{HasIOBinders} + +class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences +{ + def dp = designParameters + + val chiptop = LazyModule(p(BuildTop)(p)) + + val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head + val harnessSysPLL = dp(PLLFactoryKey) + val harnessSysPLLNode = harnessSysPLL() + println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz") + val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler()) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode + + harnessSysPLLNode := clockOverlay.overlayOutput.node + + val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0)))) + val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + + val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay] + val ddrInParams = chiptop match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(ddrInParams.master)) + val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4)) + ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient + + val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput())) + val all_leds = ledOverlays.map(_.overlayOutput.led) + val status_leds = all_leds.take(3) + val other_leds = all_leds.drop(3) + + def buildtopClock = dutClock.in.head._1.clock + def buildtopReset = dutClock.in.head._1.reset + def success = { require(false, "Unused"); false.B } + + InModuleBody { + clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin + + val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock + + // Blink the status LEDs for sanity + withClock(clk_100mhz) { + val period = (BigInt(100) << 20) / status_leds.size + val counter = RegInit(0.U(log2Ceil(period).W)) + val on = RegInit(0.U(log2Ceil(status_leds.size).W)) + status_leds.zipWithIndex.map { case (o,s) => o := on === s.U } + counter := Mux(counter === (period-1).U, 0.U, counter + 1.U) + when (counter === 0.U) { + on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U) + } + } + + other_leds(0) := resetPin + + harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset) + + ddrOverlay.mig.module.clock := buildtopClock + ddrOverlay.mig.module.reset := buildtopReset + ddrBlockDuringReset.module.clock := buildtopClock + ddrBlockDuringReset.module.reset := buildtopReset || !ddrOverlay.mig.module.io.port.init_calib_complete + + other_leds(6) := ddrOverlay.mig.module.io.port.init_calib_complete + + chiptop match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } + } + +} diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala new file mode 100644 index 00000000..3d86f354 --- /dev/null +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -0,0 +1,61 @@ +package chipyard.fpga.arty100t + +import chisel3._ + +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.subsystem.{PeripheryBusKey} +import freechips.rocketchip.tilelink.{TLBundle} +import freechips.rocketchip.util.{HeterogeneousBag} + +import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams} +import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort} +import sifive.blocks.devices.pinctrl.{BasePin} + +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +import chipyard._ +import chipyard.harness._ +import chipyard.iobinders.JTAGChipIO + +import testchipip._ + +class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + ports.map({ port => + val ath = th.asInstanceOf[Arty100THarness] + val freq = p(PeripheryBusKey).dtsFrequency.get + val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + withClockAndReset(th.buildtopClock, th.buildtopReset) { + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + val uart_to_serial = Module(new UARTToSerial( + freq, UARTParams(0, initBaudRate=uartBaudRate))) + val serial_width_adapter = Module(new SerialWidthAdapter( + narrowW = 8, wideW = SerialAdapter.SERIAL_TSI_WIDTH)) + serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) + + ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide) + + ath.io_uart_bb.bundle <> uart_to_serial.io.uart + ath.other_leds(1) := uart_to_serial.io.dropped + + ath.other_leds(9) := ram.module.io.adapter_state(0) + ath.other_leds(10) := ram.module.io.adapter_state(1) + ath.other_leds(11) := ram.module.io.adapter_state(2) + ath.other_leds(12) := ram.module.io.adapter_state(3) + } + }) + } +}) + +class WithArty100TDDRTL extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + require(ports.size == 1) + val artyTh = th.asInstanceOf[Arty100THarness] + val bundles = artyTh.ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> ports.head + } +}) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 6c8cb3a6..85b6ee24 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -47,7 +47,6 @@ class WithVCU118Tweaks extends Config( // io binders new WithUARTIOPassthrough ++ new WithSPIIOPassthrough ++ - new WithTLIOPassthrough ++ // other configuration new WithDefaultPeripherals ++ new chipyard.config.WithTLBackingMemory ++ // use TL backing memory diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index a1f67bcd..279f9865 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -42,11 +42,3 @@ class WithSPIIOPassthrough extends OverrideLazyIOBinder({ } } }) - -class WithTLIOPassthrough extends OverrideIOBinder({ - (system: CanHaveMasterTLMemPort) => { - val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") - io_tl_mem_pins_temp <> system.mem_tl - (Seq(io_tl_mem_pins_temp), Nil) - } -}) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 90ce51e0..9a3cc0d5 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -7,15 +7,15 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridg import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} -import sifive.fpgashells.shell.xilinx.{VCU118ShellBasicOverlays, UARTVCU118ShellPlacer, SDIOVCU118ShellPlacer, JTAGDebugBScanVCU118ShellPlacer, JTAGDebugVCU118ShellPlacer, cJTAGDebugVCU118ShellPlacer, PCIeVCU118FMCShellPlacer, PCIeVCU118EdgeShellPlacer, VCU118ShellPMOD, ChipLinkVCU118PlacedOverlay} +import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} -import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, ClockInputShellInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, SPIOverlayKey, SPIDesignInput, SPIShellInput, JTAGDebugOverlayKey, JTAGDebugShellInput, JTAGDebugBScanOverlayKey, JTAGDebugBScanShellInput, cJTAGDebugOverlayKey, cJTAGDebugShellInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, DDRShellInput} +import sifive.fpgashells.shell._ import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} +import chipyard._ import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index 6b1e9c3b..fa0513d7 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -70,7 +70,7 @@ extern "C" void cospike_cosim(long long int cycle, if (!sim) { printf("Configuring spike cosim\n"); std::vector mem_cfg; - std::vector hartids; + std::vector hartids; mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size)); for (int i = 0; i < info->nharts; i++) hartids.push_back(i); diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index bedc41f3..4d2bb8a5 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -75,7 +75,7 @@ public: void dcache_d(uint64_t sourceid, uint64_t data[8], unsigned char has_data, unsigned char grantack); void drain_stq(); bool stq_empty() { return st_q.size() == 0; }; - + ~chipyard_simif_t() { }; chipyard_simif_t(size_t icache_ways, size_t icache_sets, @@ -262,7 +262,7 @@ extern "C" void spike_tile(int hartid, char* isa, endianness_little, pmpregions, std::vector(), - std::vector(), + std::vector(), false, 0); processor_t* p = new processor_t(isa_parser, @@ -488,7 +488,7 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { } } } - + if (!found) { return false; } @@ -576,7 +576,7 @@ bool chipyard_simif_t::handle_cache_access(reg_t addr, size_t len, } } } - + #define SETIDX(ADDR) ((ADDR >> 6) & (n_sets - 1)) uint64_t setidx = SETIDX(addr); uint64_t offset = addr & (64 - 1); diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index a47b08e0..21dfe588 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -321,6 +321,27 @@ class WithSimSerial extends OverrideHarnessBinder({ } }) +class WithUARTSerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + ports.map({ port => + val freq = p(PeripheryBusKey).dtsFrequency.get + val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + withClockAndReset(th.buildtopClock, th.buildtopReset) { + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0))) + val serial_width_adapter = Module(new SerialWidthAdapter( + 8, SerialAdapter.SERIAL_TSI_WIDTH)) + ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide) + UARTAdapter.connect(Seq(uart_to_serial.io.uart), uart_to_serial.div) + serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) + th.success := false.B + } + }) + } +}) + + class WithTraceGenSuccess extends OverrideHarnessBinder({ (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index efbe542d..71eef713 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} +import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ @@ -23,6 +24,7 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import chipyard.{CanHaveMasterTLMemPort} import chipyard.clocking.{HasChipyardPRCI, DividerOnlyClockGenerator} import scala.reflect.{ClassTag} @@ -381,6 +383,15 @@ class WithCustomBootPin extends OverrideIOBinder({ }).getOrElse((Nil, Nil)) }) +class WithTLMemPunchthrough extends OverrideIOBinder({ + (system: CanHaveMasterTLMemPort) => { + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> system.mem_tl + (Seq(io_tl_mem_pins_temp), Nil) + } +}) + + class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 1ef19b39..34175d39 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -62,6 +62,9 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem val intSink = IntSinkNode(IntSinkPortSimple()) intSink := intNexus :=* ibus.toPLIC + // avoids a bug when there are no interrupt sources + ibus.fromAsync := NullIntSource() + // Need to have at least 1 driver to the tile notification sinks tileHaltXbarNode := IntSourceNode(IntSourcePortSimple()) tileWFIXbarNode := IntSourceNode(IntSourcePortSimple()) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index d8884410..240ae5cc 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -27,7 +27,6 @@ trait HasHarnessSignalReferences { def getRefClockFreq: Double = refClockFreq def buildtopClock: Clock def buildtopReset: Reset - def dutReset: Reset def success: Bool } @@ -91,7 +90,6 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign io.success := false.B - val dutReset = buildtopReset.asAsyncReset val success = io.success lazyDut match { case d: HasIOBinders => diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 191954f6..b084845e 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -28,6 +28,7 @@ class AbstractConfig extends Config( // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ + new chipyard.iobinders.WithTLMemPunchthrough ++ new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++ diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 230a3c06..7487a50e 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -21,6 +21,18 @@ class FPGemminiRocketConfig extends Config( new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) +class LeanGemminiRocketConfig extends Config( + new gemmini.LeanGemminiConfig ++ // use Lean Gemmini systolic array GEMM accelerator + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig) + +class LeanGemminiPrintfRocketConfig extends Config( + new gemmini.LeanGemminiPrintfConfig ++ // use Lean Gemmini systolic array GEMM accelerator + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig) + class HwachaRocketConfig extends Config( new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index c6f5ca22..b6677cb1 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -21,6 +21,14 @@ class TinyRocketConfig extends Config( new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new chipyard.config.AbstractConfig) +class UARTTSIRocketConfig extends Config( + new chipyard.harness.WithUARTSerial ++ + new chipyard.config.WithNoUART ++ + new chipyard.config.WithMemoryBusFrequency(10) ++ + new chipyard.config.WithPeripheryBusFrequency(10) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) + class SimAXIRocketConfig extends Config( new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index eec0d15d..ec9ff47c 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -37,6 +37,10 @@ class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) }) +class WithNoUART extends Config((site, here, up) => { + case PeripheryUARTKey => Nil +}) + class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 534259ab..c41e2716 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -2,6 +2,7 @@ package chipyard.config import freechips.rocketchip.config.{Config} import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} +import freechips.rocketchip.diplomacy.{DTSTimebase} // Replaces the L2 with a broadcast manager for maintaining coherence class WithBroadcastManager extends Config((site, here, up) => { @@ -11,3 +12,7 @@ class WithBroadcastManager extends Config((site, here, up) => { class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) }) + +class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => { + case DTSTimebase => freqMHz +}) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index d442c959..4d64a8ad 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -242,3 +242,14 @@ class WithDefaultFireSimBridges extends Config( new WithTracerVBridge ++ new WithFireSimIOCellModels ) + +// Shorthand to register all of the provided mmio-only bridges above +class WithDefaultMMIOOnlyFireSimBridges extends Config( + new WithSerialBridge ++ + new WithUARTBridge ++ + new WithBlockDeviceBridge ++ + new WithFASEDBridge ++ + new WithFireSimMultiCycleRegfile ++ + new WithFireSimFAME5 ++ + new WithFireSimIOCellModels +) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index bfdaad63..2ea848df 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -235,6 +235,18 @@ class FireSimGemminiRocketConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.GemminiRocketConfig) +class FireSimLeanGemminiRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LeanGemminiRocketConfig) + +class FireSimLeanGemminiPrintfRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LeanGemminiPrintfRocketConfig) + //********************************************************************************** // Supernode Configurations, base off chipyard's RocketConfig //********************************************************************************** @@ -282,3 +294,15 @@ class FireSimNoMemPortConfig extends Config( new testchipip.WithBackingScratchpad ++ new WithFireSimConfigTweaks ++ new chipyard.RocketConfig) + +class FireSimRocketMMIOOnlyConfig extends Config( + new WithDefaultMMIOOnlyFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.RocketConfig) + +class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config( + new WithDefaultMMIOOnlyFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LeanGemminiRocketConfig) diff --git a/generators/gemmini b/generators/gemmini index 9e478ecc..686cb15d 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 9e478ecce9e48bbc03b9bd3535d71e03a6269fba +Subproject commit 686cb15dad756887db62460968bc616392bc4341 diff --git a/generators/ibex b/generators/ibex index 5a512227..626127f2 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 5a512227d8f6d2929cc354c02d40200002e661e5 +Subproject commit 626127f229dd6dc926b7670eb4dd138f32a7940a diff --git a/generators/sha3 b/generators/sha3 index 98089ba3..8c5d2443 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 98089ba372a847d62024d36db62429a8bcdfd7ea +Subproject commit 8c5d244303694311c4e63e51915a492491a3f5c7 diff --git a/generators/testchipip b/generators/testchipip index 6e8a6842..dead693f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6e8a68424216c9a02916af16a15850f40a534a22 +Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31 diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh index 54afe983..049e3424 100755 --- a/scripts/build-toolchain-extra.sh +++ b/scripts/build-toolchain-extra.sh @@ -111,4 +111,11 @@ if [ $TOOLCHAIN == "riscv-tools" ]; then make -C $RDIR/generators/gemmini/software/libgemmini install fi +echo '==> Installing DRAMSim2 Shared Library' +cd $RDIR +git submodule update --init tools/DRAMSim2 +cd tools/DRAMSim2 +make libdramsim.so +cp libdramsim.so $RISCV/lib/ + echo "Extra Toolchain Utilities/Tests Build Complete!" diff --git a/scripts/check-tracegen.sh b/scripts/check-tracegen.sh index e2974fb1..c30447ee 100755 --- a/scripts/check-tracegen.sh +++ b/scripts/check-tracegen.sh @@ -6,25 +6,26 @@ SCRIPT_DIR=$(dirname $0) AXE_DIR=$(realpath ${SCRIPT_DIR}/../tools/axe) ROCKET_DIR=$(realpath ${SCRIPT_DIR}/../generators/rocket-chip) +TMP_DIR=$(mktemp -d -t tracegen-XXXXXXXX) TO_AXE=${ROCKET_DIR}/scripts/toaxe.py -TO_AXE_PY3=/tmp/toaxe.py +TO_AXE_PY3=${TMP_DIR}/toaxe.py AXE=${AXE_DIR}/src/axe AXE_SHRINK=${AXE_DIR}/src/axe-shrink.py -AXE_SHRINK_PY3=/tmp/axe-shrink.py +AXE_SHRINK_PY3=${TMP_DIR}/axe-shrink.py # TODO: convert scripts to py3 in src -2to3 $TO_AXE -o /tmp -n -w +2to3 $TO_AXE -o ${TMP_DIR} -n -w sed -i '30d' $TO_AXE_PY3 # remove import sets -2to3 $AXE_SHRINK -o /tmp -n -w +2to3 $AXE_SHRINK -o ${TMP_DIR} -n -w PATH=$PATH:${AXE_DIR}/src -grep '.*:.*#.*@' $1 > /tmp/clean-trace.txt -python "$TO_AXE_PY3" /tmp/clean-trace.txt > /tmp/trace.axe -result=$("$AXE" check wmo /tmp/trace.axe) +grep '.*:.*#.*@' $1 > ${TMP_DIR}/clean-trace.txt +python "$TO_AXE_PY3" ${TMP_DIR}/clean-trace.txt > ${TMP_DIR}/trace.axe +result=$("$AXE" check wmo ${TMP_DIR}/trace.axe) if [ "$result" != OK ]; then - "$AXE_SHRINK_PY3" wmo /tmp/trace.axe + "$AXE_SHRINK_PY3" wmo ${TMP_DIR}/trace.axe else echo OK fi diff --git a/scripts/config-finder.py b/scripts/config-finder.py new file mode 100755 index 00000000..a7377939 --- /dev/null +++ b/scripts/config-finder.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 + +import argparse +import subprocess +from collections import defaultdict +import re +from copy import deepcopy +import os + +cy_path = os.path.dirname(os.path.dirname(os.path.realpath(__file__))) + +# from https://gist.github.com/angstwad/bf22d1822c38a92ec0a9 +def deep_merge(a: dict, b: dict) -> dict: + """Merge two dicts and return a singular dict""" + result = deepcopy(a) + for bk, bv in b.items(): + av = result.get(bk) + if isinstance(av, dict) and isinstance(bv, dict): + result[bk] = deep_merge(av, bv) + else: + result[bk] = deepcopy(bv) + return result + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='Pretty print all configs given a filelist of scala files') + parser.add_argument('FILE', type=str, help='Filelist of scala files to search within') + parser.add_argument('-l', '--levels', default=0, type=int, help='Number of levels to recursively look for configs') + args = parser.parse_args() + + files = [] + with open(args.FILE, 'r') as f: + files = f.read().splitlines() + + cmd = ['grep', '-o', r"class \+.* \+extends \+Config"] + files + r = subprocess.run(cmd, check=True, capture_output=True) + + base_file_path_dict = defaultdict(list) + for l in r.stdout.decode("UTF-8").splitlines(): + match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) + if match: + base_file_path_dict[match.group(1)].append(match.group(2)) + + levels = [] + for level in range(args.levels): + if level == 0: + # use the base + dict_to_use = base_file_path_dict + else: + # use the level-1 dict + assert len(levels) > 0 + dict_to_use = levels[-1] + + file_path_dict = defaultdict(list) + + for configs in dict_to_use.values(): + for config in configs: + cmd = ['grep', '-o', r"class \+.* \+extends \+" + f"{config}"] + files + r = subprocess.run(cmd, capture_output=True) + + for l in r.stdout.decode("UTF-8").splitlines(): + match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) + if match: + file_path_dict[match.group(1)].append(match.group(2)) + + levels.append(file_path_dict) + + final_dict = base_file_path_dict + for dct in levels: + final_dict = deep_merge(final_dict, dct) + + print(f"Finding all one-line config. fragments (up to {args.levels} levels)\n") + for k, v in final_dict.items(): + print(f"{k.replace(cy_path, 'chipyard')}:") + for e in v: + print(f" {e}") + print("") diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 2635e059..3f939bc2 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -106,8 +106,6 @@ cd "$RDIR" software/coremark \ software/firemarshal \ software/spec2017 \ - vlsi/hammer-cadence-plugins \ - vlsi/hammer-synopsys-plugins \ vlsi/hammer-mentor-plugins \ fpga/fpga-shells do diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh index 6be7f927..8925fb1a 100755 --- a/scripts/init-vlsi.sh +++ b/scripts/init-vlsi.sh @@ -12,10 +12,6 @@ fi # Initialize HAMMER CAD-plugins if [[ $1 != *openroad* ]] && [[ $2 != *openroad* ]]; then - git submodule update --init --recursive vlsi/hammer-cadence-plugins - pip install -e vlsi/hammer-cadence-plugins - git submodule update --init --recursive vlsi/hammer-synopsys-plugins - pip install -e vlsi/hammer-synopsys-plugins git submodule update --init --recursive vlsi/hammer-mentor-plugins pip install -e vlsi/hammer-mentor-plugins fi diff --git a/sims/firesim b/sims/firesim index 9d3462ed..68e51138 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9d3462ed1357cc198be8485ae57635b9651999d5 +Subproject commit 68e5113887d36e87bb6202e7fd1e7e51e786a91b diff --git a/sims/xcelium/.gitignore b/sims/xcelium/.gitignore new file mode 100644 index 00000000..254f02f7 --- /dev/null +++ b/sims/xcelium/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +*Makefile \ No newline at end of file diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile new file mode 100644 index 00000000..12b31087 --- /dev/null +++ b/sims/xcelium/Makefile @@ -0,0 +1,140 @@ +######################################################################################### +# xcelium makefile +######################################################################################### + +define CAD_INFO_HEADER +# -------------------------------------------------------------------------------- +# This script was written and developed by Chipyard at UC Berkeley; however, the +# underlying commands and reports are copyrighted by Cadence. We thank Cadence for +# granting permission to share our research to help promote and foster the next +# generation of innovators. +# -------------------------------------------------------------------------------- +endef + +export CAD_INFO_HEADER + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ../..) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +######################################################################################### +# name of simulator (used to generate *.f arguments file) +######################################################################################### +sim_name = xrun + +######################################################################################### +# xcelium simulator types and rules +######################################################################################### +sim_prefix = simx +sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) +sim_debug = $(sim)-debug +sim_workdir = $(build_dir)/xcelium.d +sim_run_tcl = $(build_dir)/xcelium_run.tcl +sim_debug_run_tcl = $(build_dir)/xcelium_debug_run.tcl + +include $(base_dir)/xcelium.mk + +.PHONY: default debug +default: $(sim) +debug: $(sim_debug) + +######################################################################################### +# simulation requirements +######################################################################################### +SIM_FILE_REQS += \ + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v + +# copy files but ignore *.h files in *.f since xcelium has -Wcxx include +$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) + cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR) + $(foreach file,\ + $(SIM_FILE_REQS),\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;)) + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# xcelium binary and arguments +######################################################################################### +XCELIUM = xrun +XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES) + +######################################################################################### +# xcelium build paths +######################################################################################### +model_dir = $(build_dir)/$(long_name) +model_dir_debug = $(build_dir)/$(long_name).debug + + +######################################################################################### +# xcelium simulator rules +######################################################################################### + +$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) + rm -rf $(model_dir) + $(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS) + +$(sim_run_tcl): $(sim_workdir) + echo "$$CAD_INFO_HEADER" > $(sim_run_tcl) + echo "run" >> $(sim_run_tcl) + echo "exit" >> $(sim_run_tcl) + +# The system libstdc++ may not link correctly with some of our dynamic libs, so +# force loading the conda one (if present) with LD_PRELOAD +$(sim): $(sim_workdir) $(sim_run_tcl) + echo "#!/usr/bin/env bash" > $(sim) + echo "$$CAD_INFO_HEADER" >> $(sim) + cat arg-reshuffle >> $(sim) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim) + chmod +x $(sim) + +$(sim_debug_run_tcl): $(sim_workdir) + echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl) + echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl) + echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl) + echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl) + echo "run" >> $(sim_debug_run_tcl) + echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl) + echo "exit" >> $(sim_debug_run_tcl) + + +$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl) + echo "#!/usr/bin/env bash" > $(sim_debug) + echo "$$CAD_INFO_HEADER" >> $(sim_debug) + cat arg-reshuffle >> $(sim_debug) + echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug) + echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug) + chmod +x $(sim_debug) + + +######################################################################################### +# create vcd rules +######################################################################################### +.PRECIOUS: $(output_dir)/%.vcd %.vcd +$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + +######################################################################################### +# general cleanup rules +######################################################################################### +.PHONY: clean clean-sim clean-sim-debug +clean: + rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log + +clean-sim-debug: + rm -rf $(model_dir_debug) $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log diff --git a/sims/xcelium/arg-reshuffle b/sims/xcelium/arg-reshuffle new file mode 100755 index 00000000..08176864 --- /dev/null +++ b/sims/xcelium/arg-reshuffle @@ -0,0 +1,30 @@ + +# this is a wrapper that is copied into xcelium sim run scripts that +# re-maps arguments from the argument pattern used by other +# simulators (vcs, verilator) to the pattern required by xcelium. +# +# mainly: +# * +vcdfile=VAL -> XCELIUM_WAVEFORM_FLAG=VAL, to be passed in as env var +# * arguments not prefixed with a + or - are treated as the arguments to +# the target and are passed in instead with the +target-argument plusarg + +regular_args="" +target_args="+permissive" +for var in "$@" +do + if [[ $var = -* ]] || [[ $var = +* ]] + then + if [[ $var = +vcdfile=* ]] + then + XCELIUM_WAVEFORM_FLAG=${var/+vcdfile=/""} + else + regular_args="$regular_args $var" + fi + else + target_args="$target_args +target-argument=$var" + fi +done +target_args="$target_args +permissive-off" + +INPUT_ARGS="$regular_args $target_args" + diff --git a/software/firemarshal b/software/firemarshal index 8e02b02d..12784a42 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 8e02b02d14f2d67bb8d62e0a92e097bbea45994f +Subproject commit 12784a42cb1b2188536ef5bfc123f800374d3177 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index e7d6aff1..34bebfe3 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit e7d6aff19a071a059f1b9c2328ee4dac83bc677a +Subproject commit 34bebfe31183289b5428b9a363a4596750030d3f diff --git a/tools/chisel-testers b/tools/chisel-testers deleted file mode 160000 index ce4e027e..00000000 --- a/tools/chisel-testers +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ce4e027e5f3d871df59236b8471ea3e5be40130e diff --git a/variables.mk b/variables.mk index 1b2d0d1c..8e171712 100644 --- a/variables.mk +++ b/variables.mk @@ -154,6 +154,7 @@ BTL_CLASSPATH_TARGETS ?= $(subst :, ,$(BTL_CLASSPATH)) FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extra.anno.json +CHISEL_LOG_FILE ?= $(build_dir)/$(long_name).chisel.log # chisel anno modification output MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json @@ -212,7 +213,7 @@ sim_common_files ?= $(build_dir)/sim_files.common.f ######################################################################################### JAVA_HEAP_SIZE ?= 8G JAVA_TMP_DIR ?= $(base_dir)/.java_tmp -export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(JAVA_TMP_DIR) +export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(JAVA_TMP_DIR) ######################################################################################### # default sbt launch command @@ -222,6 +223,7 @@ SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) # passes $(JAVA_TOOL_OPTIONS) from env to java SBT ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) + # (1) - classpath of the fat jar # (2) - main class # (3) - main class arguments diff --git a/vlsi/Makefile b/vlsi/Makefile index ab8438d5..8259e7a6 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -46,9 +46,9 @@ VLSI_MODEL_DUT_NAME ?= chiptop # If overriding, this should be relative to $(vlsi_dir) VLSI_OBJ_DIR ?= build ifneq ($(CUSTOM_VLOG),) - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP) else - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP) endif ######################################################################################### @@ -118,6 +118,12 @@ endif $(SYN_CONF): $(VLSI_RTL) mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " input_files:" >> $@ + for x in $$(cat $(VLSI_RTL)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 8aafe8c0..dbcadab0 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints: right: 0 top: 0 bottom: 0 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 550 y: 25 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1" type: hardmacro x: 550 y: 270 orientation: "r0" top_layer: "M4" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2" type: hardmacro x: 675 y: 25 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3" type: hardmacro x: 675 y: 270 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 125 y: 150 orientation: "my" top_layer: "M4" master: "SRAM1RW64x21" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 0 y: 25 orientation: "my" top_layer: "M4" master: "SRAM1RW1024x32" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" - type: hardmacro - x: 0 - y: 260 - orientation: "my" - top_layer: "M4" - master: "SRAM1RW1024x37" # Pin placement constraints vlsi.inputs.pin_mode: generated diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index 6edca4d6..b2ecfb26 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,149 +2,18 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "5ns", uncertainty: "1ns"} + {name: "clock_clock", period: "30ns", uncertainty: "2ns"} ] -# Power Straps -par.power_straps_mode: generate -par.generate_power_straps_method: by_tracks -par.blockage_spacing: 40.0 -par.blockage_spacing_top_layer: met4 -par.generate_power_straps_options: - by_tracks: - strap_layers: - - met4 - - met5 - pin_layers: - - met5 - blockage_spacing_met2: 4.0 - blockage_spacing_met4: 2.0 - track_width: 3 - track_width_met5: 1 - track_spacing: 5 - track_start: 10 - track_start_met5: 1 - power_utilization: 0.1 - power_utilization_met4: 0.1 - power_utilization_met5: 0.1 - # Placement Constraints -vlsi.inputs.placement_constraints: - - path: "ChipTop" - type: toplevel - x: 0 - y: 0 - width: 4000 - height: 2500 - margins: - left: 0 - right: 0 - top: 0 - bottom: 0 - - # Place data cache SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 100 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" - type: hardmacro - x: 50 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" - type: hardmacro - x: 50 - y: 1300 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" - type: hardmacro - x: 50 - y: 1900 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" - type: hardmacro - x: 1000 - y: 1900 - orientation: r0 - - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" - type: hardmacro - x: 1000 - y: 1300 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" - type: hardmacro - x: 1000 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" - type: hardmacro - x: 1000 - y: 100 - orientation: r0 - - # Place instruction cache SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 3250 - y: 100 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" - type: hardmacro - x: 3250 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" - type: hardmacro - x: 3450 - y: 1300 - orientation: r0 - - # Place L2 TLB SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" - type: hardmacro - x: 2000 - y: 1300 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" - type: hardmacro - x: 2000 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" - type: hardmacro - x: 2750 - y: 1300 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" - type: hardmacro - x: 2750 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" - type: hardmacro - x: 3460 - y: 1900 - orientation: "r0" - -# Pin placement constraints -vlsi.inputs.pin_mode: generated -vlsi.inputs.pin.generate_mode: semi_auto -vlsi.inputs.pin.assignments: [ - {pins: "*", layers: ["met2", "met4"], side: "bottom"} -] +# If overriding the placement constraints in example-sky130.yml, +# ensure one of the toplevel margin sides corresponding with the power pin metal layers +# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail). +# For example, in example-sky130.yml we set +# par.generate_power_straps_options.by_tracks.pin_layers: 'met5' # horizontal layer +# therefore we must also set: +# vlsi.inputs.placement_constraints: +# - path: "ChipTop" +# ... +# margins: +# right: 0 # or left: 0 \ No newline at end of file diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml new file mode 100644 index 00000000..752facfd --- /dev/null +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -0,0 +1,60 @@ +# Override configurations in ../example-sky130.yml and example-designs + +# Specify clock signals +# Rocket/RocketTile names clock signal "clock" instead of "clock_clock" +vlsi.inputs.clocks: [ + {name: "clock", period: "30ns", uncertainty: "3ns"} +] + +# Placement Constraints +# Placement Constraints +vlsi.inputs.placement_constraints: + - path: "RocketTile" + type: toplevel + x: 0 + y: 0 + width: 4000 + height: 3000 + margins: + left: 10 + right: 0 + top: 10 + bottom: 10 + + # Place SRAM memory instances + # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag + # data cache + - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 50 + orientation: r90 + - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 450 + orientation: r90 + - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 850 + orientation: r90 + - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 1250 + orientation: r90 + + # tag array + - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 1600 + orientation: r90 + + # instruction cache + - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 2100 + orientation: r90 diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 62c2aca4..b52266b4 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,9 +3,42 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_clock", period: "30ns", uncertainty: "1ns"} + {name: "clock_clock", period: "50ns", uncertainty: "2ns"} ] +# Flow parameters that yield a routable design with reasonable timing +par.openroad: + timing_driven: true # set to false to drastically speed up runs + create_archive_mode: none + + write_reports: true # set to false to slightly speed up runs + + floorplan_mode: generate + + macro_placement.halo: [50, 50] + + global_placement.timing_driven: true + global_placement.routability_driven: true + + global_placement.placement_padding: 6 + detailed_placement.placement_padding: 4 + clock_tree.placement_padding: 2 + clock_tree_resize.placement_padding: 0 + + clock_tree_resize.setup_margin: 0.0 + clock_tree_resize.hold_margin: 0.20 + global_route_resize.hold_margin: 0.60 + clock_tree_resize.hold_max_buffer_percent: 80 + + global_placement.routing_adjustment: 0.5 + global_route.routing_adjustment: 0.3 + global_route_resize.routing_adjustment: 0.2 + +# DRC/LVS configuration +drc.magic.generate_only: true +lvs.netgen.generate_only: true + + # Placement Constraints vlsi.inputs.placement_constraints: - path: "ChipTop" @@ -13,78 +46,47 @@ vlsi.inputs.placement_constraints: x: 0 y: 0 width: 4000 - height: 2500 + height: 3000 margins: left: 10 - right: 10 + right: 0 top: 10 bottom: 10 - # Place data cache SRAM instances - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0" + # Place SRAM memory instances + # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag + # data cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 100 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0" + y: 50 + orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 700 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0" + y: 450 + orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 1300 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0" + y: 850 + orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 1900 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0" + y: 1250 + orientation: r90 + + # tag array + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro - x: 1000 - y: 1900 - orientation: r0 + x: 50 + y: 1600 + orientation: r90 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0" + # instruction cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" type: hardmacro - x: 1000 - y: 1300 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0" - type: hardmacro - x: 1000 - y: 700 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0" - type: hardmacro - x: 1000 - y: 100 - orientation: r0 - - # Place instruction cache SRAM instances - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0" - type: hardmacro - x: 3250 - y: 100 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0" - type: hardmacro - x: 3250 - y: 700 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0" - type: hardmacro - x: 3450 - y: 1300 - orientation: r0 + x: 50 + y: 2100 + orientation: r90 diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 39a31c01..5481c4a8 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -7,7 +7,7 @@ vlsi.core.max_threads: 12 # Technology paths technology.sky130: sky130A: "/path/to/sky130A" - openram_lib: "/path/to/sky130_sram_macros" + sram22_sky130_macros: "/path/to/sram22_sky130_macros" # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path sky130_nda: "/path/to/skywater-src-nda" @@ -20,31 +20,55 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "10ns", uncertainty: "1ns"} + {name: "clock_clock", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow vlsi.core.build_system: make + # Placement Constraints vlsi.inputs.placement_constraints: - path: "ChipTop" type: toplevel x: 0 y: 0 - width: 3500 - height: 2500 + width: 4000 + height: 3000 margins: left: 10 - right: 10 + right: 0 top: 10 bottom: 10 + # Place SRAM memory instances + # data cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 50 + orientation: r90 + + # tag array + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 1600 + orientation: r90 + + # instruction cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 2100 + orientation: r90 + + # Power Straps par.power_straps_mode: generate par.generate_power_straps_method: by_tracks -par.blockage_spacing: 40.0 -par.blockage_spacing_top_layer: met4 +par.blockage_spacing: 2.0 +par.blockage_spacing_top_layer: met3 par.generate_power_straps_options: by_tracks: strap_layers: @@ -63,6 +87,7 @@ par.generate_power_straps_options: power_utilization_met4: 0.1 power_utilization_met5: 0.1 + # Pin placement constraints vlsi.inputs.pin_mode: generated vlsi.inputs.pin.generate_mode: semi_auto @@ -70,5 +95,6 @@ vlsi.inputs.pin.assignments: [ {pins: "*", layers: ["met2", "met4"], side: "bottom"} ] + # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler" diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins deleted file mode 160000 index f9e323bd..00000000 --- a/vlsi/hammer-cadence-plugins +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f9e323bd64b8cc79ab810b9761226e9de768f237 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins deleted file mode 160000 index e53fa5c5..00000000 --- a/vlsi/hammer-synopsys-plugins +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e53fa5c51f37937c83df3b004693552f59015c90 diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 5623f9d3..1f5b530d 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(cat $(sim_common_files)); do \ + for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 9b69b149..6b970fcb 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -2,6 +2,7 @@ # makefile variables for Hammer tutorials ######################################################################################### tutorial ?= none +EXTRA_CONFS ?= # TODO: eventually have asap7 commercial/openroad tutorial flavors ifeq ($(tutorial),asap7) @@ -9,7 +10,7 @@ ifeq ($(tutorial),asap7) CONFIG ?= TinyRocketConfig TOOLS_CONF ?= example-tools.yml TECH_CONF ?= example-asap7.yml - INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF) + DESIGN_CONFS ?= VLSI_OBJ_DIR ?= build-asap7-commercial endif @@ -18,9 +19,9 @@ ifeq ($(tutorial),sky130-commercial) CONFIG ?= TinyRocketConfig TOOLS_CONF ?= example-tools.yml TECH_CONF ?= example-sky130.yml - DESIGN_CONF ?= example-designs/sky130-commercial.yml - EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) - INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) + DESIGN_CONFS ?= example-designs/sky130-commercial.yml \ + $(if $(filter $(VLSI_TOP),Rocket), \ + example-designs/sky130-rocket.yml, ) VLSI_OBJ_DIR ?= build-sky130-commercial endif @@ -29,10 +30,14 @@ ifeq ($(tutorial),sky130-openroad) CONFIG ?= TinyRocketConfig TOOLS_CONF ?= example-openroad.yml TECH_CONF ?= example-sky130.yml - DESIGN_CONF ?= example-designs/sky130-openroad.yml - EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) - INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) + DESIGN_CONFS ?= example-designs/sky130-openroad.yml \ + $(if $(filter $(VLSI_TOP),Rocket), \ + example-designs/sky130-rocket.yml) \ + $(if $(filter $(VLSI_TOP),RocketTile), \ + example-designs/sky130-openroad-rockettile.yml, ) VLSI_OBJ_DIR ?= build-sky130-openroad # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. - ENABLE_CUSTOM_FIRRTL_PASS = 1 + ENABLE_YOSYS_FLOW = 1 endif + +INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) diff --git a/xcelium.mk b/xcelium.mk new file mode 100644 index 00000000..3d9ed5ab --- /dev/null +++ b/xcelium.mk @@ -0,0 +1,65 @@ + +WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd + +# If ntb_random_seed unspecified, xcelium uses 1 as constant seed. +# Set ntb_random_seed_automatic to actually get a random seed +ifdef RANDOM_SEED +SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) +else +SEED_FLAG=+ntb_random_seed_automatic +endif + +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +include $(base_dir)/sims/common-sim-flags.mk + + +XC_CXX_PREFIX=-Wcxx, +XC_LD_PREFIX=-Wld, + +REMOVE_RPATH=-Wl,-rpath% + +XCELIUM_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS)) +XCELIUM_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS))) + +XCELIUM_COMMON_ARGS = \ + -64bit \ + -xmlibdirname $(sim_workdir) \ + -l /dev/null \ + -log_xmsc_run /dev/null + +XCELIUM_CC_OPTS = \ + $(XCELIUM_CXXFLAGS) \ + $(XCELIUM_LDFLAGS) \ + -enable_rpath + +XCELIUM_NONCC_OPTS = \ + -fast_recompilation \ + -top $(TB) \ + -sv \ + -ALLOWREDEFINITION \ + -timescale 1ns/10ps \ + -define INTCNOPWR \ + -define INTC_NO_PWR_PINS \ + -define INTC_EMULATION \ + -f $(sim_common_files) \ + -glsperf \ + -notimingchecks \ + -delay_mode zero + +PREPROC_DEFINES = \ + -define XCELIUM \ + -define CLOCK_PERIOD=$(CLOCK_PERIOD) \ + -define RESET_DELAY=$(RESET_DELAY) \ + -define PRINTF_COND=$(TB).printf_cond \ + -define STOP_COND=!$(TB).reset \ + -define MODEL=$(MODEL) \ + -define RANDOMIZE_MEM_INIT \ + -define RANDOMIZE_REG_INIT \ + -define RANDOMIZE_GARBAGE_ASSIGN \ + -define RANDOMIZE_INVALID_ASSIGN +