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Add option to add async queues between chip-serialIO and harness serdes

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This commit is contained in:
Jerry Zhao
2021-03-15 02:16:18 -07:00
parent f52822ff7a
commit c27c9d5d18
2 changed files with 19 additions and 7 deletions
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24
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -238,23 +238,35 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
}) })
class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system) implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port => ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) val bits = if (asyncQueue) {
SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
} else {
port.bits
}
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser) SerialAdapter.tieoff(ram.module.io.tsi_ser)
}) })
} }
}) })
class WithSimSerial extends OverrideHarnessBinder({ class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system) implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port => ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) val bits = if (asyncQueue) {
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool) SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
when (success) { th.success := true.B } } else {
port.bits
}
withClockAndReset(th.harnessClock, th.harnessReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)
when (success) { th.success := true.B }
}
}) })
} }
}) })

2
generators/testchipip

Submodule generators/testchipip updated: 282ca2e25e...6e2db28a16