From c179f53ed09781f3ff655114e2e2e30dd9c71231 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 8 Oct 2022 10:48:45 -0700 Subject: [PATCH] Fix comments --- sims/vcs/Makefile | 2 +- sims/verilator/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index f4603bfc..0b71cd30 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -32,7 +32,7 @@ default: $(sim) debug: $(sim_debug) ######################################################################################### -# simulaton requirements +# simulation requirements ######################################################################################### SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 10674823..2b902467 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -50,7 +50,7 @@ SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ -# the following files are needed for emulator.cc to compile (even if they aren't included in RTL) +# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build) SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \