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spelling check | better heading for accelerators

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abejgonzalez
2019-05-27 19:07:55 -07:00
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docs/Simulation/Commercial-Simulators.rst
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Commericial Software RTL Simulators
Commercial Software RTL Simulators
==============================
VCS
-----------------------
`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`__ is a commercial RTL simulator developed by Synopsys.
It requires commerical licenses.
It requires commercial licenses.
The REBAR framework can compile and execute simulations using VCS.
VCS simulation will generally compile faster than Verilator simulations.
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./simulator-<yourproject>-<yourconfig> ...
If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
This will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
If you have Synopsys licenses, we recommend using the DVE waveform viewer.
Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.

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docs/Simulation/index.rst
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Simulators
=======================
REBAR provides support and intergration for multiple simulation flows, for various user levels and requirments.
REBAR provides support and integration for multiple simulation flows, for various user levels and requirements.
In the majority of cases during a digital design development process, a simple software RTL simulation will do.
When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution.
The following pages provide detailed information about the simulation possibilities within the REBAR framework.