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Make BootAddrReg optional

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This commit is contained in:
Jerry Zhao
2023-05-08 14:36:36 -07:00
parent 7b8cb001ee
commit c148f1daf1
3 changed files with 4 additions and 2 deletions
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2
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink._
// DOC include start: DigitalTop // DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device

2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -46,6 +46,8 @@ class AbstractConfig extends Config(
// This should get replaced with a PLL-like config instead // This should get replaced with a PLL-like config instead
new chipyard.clocking.WithDividerOnlyClockGenerator ++ new chipyard.clocking.WithDividerOnlyClockGenerator ++
new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity

2
generators/testchipip

Submodule generators/testchipip updated: 363b683552...ebf61569c5