Update docs

docs/Generators/Gemmini.rst

@@ -9,7 +9,7 @@ To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConf
 
 The example Chipyard config includes the following example SoC configuration which includes Gemmini:
 
-.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala
     :language: scala
     :start-after: DOC include start: GemminiRocketConfig
     :end-before: DOC include end: GemminiRocketConfig
@@ -42,7 +42,7 @@ Major parameters of interest include:
 
 * DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``): Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters.
 
-Software
+Gemmini Software
 ------------------
 
 The Gemmini non-standard ISA extension is specified in the `Gemmini repository <https://github.com/ucb-bar/gemmini/blob/master/README.md>`__.

docs/Generators/Rocket-Chip.rst

@@ -58,8 +58,8 @@ The ``PeripheryBus`` attaches additional peripherals like the NIC and Block Devi
 It can also optionally expose an external AXI4 port, which can be attached to
 vendor-supplied AXI4 IP.
 
-To learn more about adding MMIO peripherals, check out the :ref:`MMIO Peripheral`
-section of :ref:`Adding an Accelerator/Device`.
+To learn more about adding MMIO peripherals, check out the :ref:`mmio-accelerators`
+section.
 
 DMA
 ---
@@ -68,5 +68,4 @@ You can also add DMA devices that read and write directly from the memory
 system. These are attached to the ``FrontendBus``. The ``FrontendBus`` can also
 connect vendor-supplied AXI4 DMA devices through an AXI4 to TileLink converter.
 
-To learn more about adding DMA devices, see the :ref:`Adding a DMA port` section
-of :ref:`Adding an Accelerator/Device`.
+To learn more about adding DMA devices, see the :ref:`dma-devices` section.

docs/Generators/SHA3.rst

@@ -72,7 +72,7 @@ it can be mixed into a Rocket or BOOM core by overriding the
 generator. An example configuration highlighting the use of
 this mixin is shown here:
 
-.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala
    :language: scala
    :start-after: DOC include start: Sha3Rocket
    :end-before: DOC include end: Sha3Rocket

docs/Generators/SiFive-Generators.rst

@@ -18,7 +18,7 @@ Peripheral Devices
 These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
 To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. 
 
-.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigMixins.scala
     :language: scala
     :start-after: DOC include start: gpio mixin
     :end-before: DOC include end: gpio mixin
@@ -26,12 +26,12 @@ To integrate one of these devices in your SoC, you will need to define a custom
 Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC.
 When adding a top-level IO, you should also be aware of whether it interacts with the test-harness.
 
-This example instantiates a top-level module with include GPIO ports (``TopWithGPIO``), and then ties-off the GPIO port inputs to 0 (``false.B``).
+This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``).
 
 
 Finally, you add the relevant config mixin to the SoC config. For example:
 
-.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala
     :language: scala
     :start-after: DOC include start: GPIORocketConfig
     :end-before: DOC include end: GPIORocketConfig

docs/Generators/TestChipIP.rst

@@ -22,9 +22,7 @@ The block device controller provides a generic interface for secondary storage.
 This device is primarily used in FireSim to interface with a block device
 software simulation model. The default Linux configuration in `firesim-software <https://github.com/firesim/firesim-software>`_
 
-To add a block device to your design, add ``HasPeripheryBlockDevice`` to your
-lazy module and ``HasPeripheryBlockDeviceModuleImp`` to the implementation.
-Then add the ``WithBlockDevice`` config mixin to your configuration.
+To add a block device to your design, add the ``WithBlockDevice`` config mixin to your configuration.
 
 
 TileLink SERDES
@@ -71,5 +69,4 @@ during Linux boot). In addition to working with ``stdin/stdout`` of the host, it
 output a UART log to a particular file using ``+uartlog=<NAME_OF_FILE>`` during simulation.
 
 By default, this UART Adapter is added to all systems within Chipyard by adding the
-``CanHavePeripheryUARTWithAdapter`` and ``CanHavePeripheryUARTWithAdapterImp`` traits to the ``Top`` system.
-These traits add a SiFive UART to the system as well as add the UART Adapter to the TestHarness.
+``WithUART`` and ``WithUARTAdapter`` configs.

docs/Generators/index.rst

@@ -1,6 +1,6 @@
 .. _generator-index:
 
-Generators
+Included RTL Generators
 ============================
 
 A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL.