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Jerry Zhao
2020-02-13 11:40:10 -08:00
parent 0f56c4ce44
commit c12819eb52
28 changed files with 247 additions and 301 deletions
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docs/Chipyard-Basics/Development-Ecosystem.rst
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@@ -16,7 +16,7 @@ Chisel is an embedded language within Scala that provides a set of libraries to
FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more!
These two tools in combination allow quick design space exploration and development of new RTL.
Generators
RTL Generators
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Within this repository, all of the Chisel RTL is written as generators.