WIP
This commit is contained in:
David Biancolin
205
generators/firechip/src/main/scala/TargetConfigs.scala
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205
generators/firechip/src/main/scala/TargetConfigs.scala
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package firesim.firesim
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import java.io.File
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import chisel3.util.{log2Up}
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import freechips.rocketchip.config.{Parameters, Config}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.devices.debug.DebugModuleParams
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import boom.system.BoomTilesKey
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import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import icenet._
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class WithBootROM extends Config((site, here, up) => {
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case BootROMParams => {
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val rebarBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
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val firesimBootROM = new File(s"./target-rtl/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
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val bootROMPath = if (rebarBootROM.exists()) {
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rebarBootROM.getAbsolutePath()
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} else {
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firesimBootROM.getAbsolutePath()
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}
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BootROMParams(contentFileName = bootROMPath)
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}
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})
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class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => {
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case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
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})
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class WithUARTKey extends Config((site, here, up) => {
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case PeripheryUARTKey => List(UARTParams(
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address = BigInt(0x54000000L),
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nTxEntries = 256,
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nRxEntries = 256))
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})
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class WithNICKey extends Config((site, here, up) => {
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case NICKey => NICConfig(
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inBufFlits = 8192,
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ctrlQueueDepth = 64)
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})
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class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
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core = tile.core.copy(
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nL2TLBEntries = entries
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)
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))
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})
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class WithPerfCounters extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
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core = tile.core.copy(nPerfCounters = 29)
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))
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})
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class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
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case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
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core = tile.core.copy(nL2TLBEntries = entries)
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))
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})
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// Disables clock-gating; doesn't play nice with our FAME-1 pass
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class WithoutClockGating extends Config((site, here, up) => {
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case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false)
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})
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// Testing configurations
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// This enables printfs used in testing
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class WithScalaTestFeatures extends Config((site, here, up) => {
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case PrintTracePort => true
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})
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/*******************************************************************************
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* Full TARGET_CONFIG configurations. These set parameters of the target being
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* simulated.
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*
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* In general, if you're adding or removing features from any of these, you
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* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
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* will store this name as part of the tags for the AGFI, so that later you can
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* reconstruct what is in a particular AGFI. These tags are also used to
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* determine which driver to build.
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*******************************************************************************/
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class FireSimRocketChipConfig extends Config(
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new WithBootROM ++
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
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new WithExtMemSize(0x400000000L) ++ // 16GB
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new WithoutTLMonitors ++
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new WithUARTKey ++
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new WithNICKey ++
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new WithBlockDevice ++
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new WithRocketL2TLBs(1024) ++
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new WithPerfCounters ++
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new WithoutClockGating ++
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new freechips.rocketchip.system.DefaultConfig)
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class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i))
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})
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// single core config
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class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig)
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// dual core config
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class FireSimRocketChipDualCoreConfig extends Config(
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new WithNDuplicatedRocketCores(2) ++
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new FireSimRocketChipSingleCoreConfig)
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// quad core config
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class FireSimRocketChipQuadCoreConfig extends Config(
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new WithNDuplicatedRocketCores(4) ++
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new FireSimRocketChipSingleCoreConfig)
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// hexa core config
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class FireSimRocketChipHexaCoreConfig extends Config(
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new WithNDuplicatedRocketCores(6) ++
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new FireSimRocketChipSingleCoreConfig)
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// octa core config
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class FireSimRocketChipOctaCoreConfig extends Config(
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new WithNDuplicatedRocketCores(8) ++
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new FireSimRocketChipSingleCoreConfig)
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class FireSimBoomConfig extends Config(
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new WithBootROM ++
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
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new WithExtMemSize(0x400000000L) ++ // 16GB
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new WithoutTLMonitors ++
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new WithUARTKey ++
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new WithNICKey ++
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new WithBlockDevice ++
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new WithBoomL2TLBs(1024) ++
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new WithoutClockGating ++
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// Using a small config because it has 64-bit system bus, and compiles quickly
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new boom.system.SmallBoomConfig)
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// A safer implementation than the one in BOOM in that it
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// duplicates whatever BOOMTileKey.head is present N times. This prevents
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// accidentally (and silently) blowing away configurations that may change the
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// tile in the "up" view
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class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => {
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case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i))
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case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
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})
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class FireSimBoomDualCoreConfig extends Config(
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new WithNDuplicatedBoomCores(2) ++
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new FireSimBoomConfig)
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class FireSimBoomQuadCoreConfig extends Config(
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new WithNDuplicatedBoomCores(4) ++
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new FireSimBoomConfig)
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//**********************************************************************************
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//* Supernode Configurations
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//*********************************************************************************/
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class WithNumNodes(n: Int) extends Config((pname, site, here) => {
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case NumNodes => n
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})
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class SupernodeFireSimRocketChipConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipConfig)
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class SupernodeFireSimRocketChipSingleCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipSingleCoreConfig)
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class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config(
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new WithNumNodes(6) ++
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new WithExtMemSize(0x40000000L) ++ // 1GB
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new FireSimRocketChipSingleCoreConfig)
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class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config(
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new WithNumNodes(8) ++
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new WithExtMemSize(0x40000000L) ++ // 1GB
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new FireSimRocketChipSingleCoreConfig)
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class SupernodeFireSimRocketChipDualCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipDualCoreConfig)
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class SupernodeFireSimRocketChipQuadCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipQuadCoreConfig)
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class SupernodeFireSimRocketChipHexaCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipHexaCoreConfig)
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class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipOctaCoreConfig)
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