wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump firechip

Browse Source
This commit is contained in:
Jerry Zhao
2024-01-26 18:40:08 -08:00
parent 205a1f2029
commit bf010668e3
2 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import sifive.blocks.devices.uart._
import testchipip.serdes.{ExternalSyncSerialIO}
import testchipip.serdes.{ExternalSyncPhitIO}
import testchipip.tsi.{SerialRAM}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
@@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
case (th: FireSim, port: SerialTLPort, chipId: Int) => {
port.io match {
case io: ExternalSyncSerialIO => {
case io: ExternalSyncPhitIO => {
io.clock_in := th.harnessBinderClock
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
ram.io.ser.in <> io.out