add test case

2019-10-28 13:45:05 -07:00
parent 7f0828cb30
commit be3b05a909
3 changed files with 143 additions and 31 deletions
--- a/macros/src/test/resources/lib-MaskPortTest.json
+++ b/macros/src/test/resources/lib-MaskPortTest.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type" : "sram",
+    "name" : "fake_mem",
+    "width" : 64,
+    "depth" : "512",
+    "mux" : 4,
+    "family" : "1rw",
+    "ports" : [ {
+        "address port name" : "addr",
+        "address port polarity" : "active high",
+        "clock port name" : "clk",
+        "clock port polarity" : "positive edge",
+        "write enable port name" : "wen",
+        "write enable port polarity" : "active high",
+        "read enable port name" : "ren",
+        "read enable port polarity" : "active high",
+        "output port name" : "dataout",
+        "output port polarity" : "active high",
+        "input port name" : "datain",
+        "input port polarity" : "active high",
+        "mask port name" : "mport",
+        "mask port polarity" : "active low",
+        "mask granularity" : 1
+    } ]
+  }
+]