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Merge remote-tracking branch 'origin/main' into bumprc

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This commit is contained in:
Jerry Zhao
2023-05-26 23:00:43 -07:00
parent 3f06dbc280 c1ad70c10f
commit bdff878643
17 changed files with 178 additions and 129 deletions
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2
sims/vcs/Makefile
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@@ -93,7 +93,7 @@ $(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-* ucli.key
clean-sim:
rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key

4
sims/vcs/vcs.mk
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@@ -5,9 +5,9 @@ HELP_SIMULATION_VARIABLES += \
" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB."
ifndef USE_VPD
WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
get_waveform_flag=+fsdbfile=$(1).fsdb
else
WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
get_waveform_flag=+vcdplusfile=$(1).vpd
endif
# If ntb_random_seed unspecified, vcs uses 1 as constant seed.

4
sims/verilator/Makefile
View File

@@ -96,7 +96,7 @@ USE_FST ?= 0
TRACING_OPTS := $(if $(filter $(USE_FST),0),\
--trace,--trace-fst --trace-threads 1)
# TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar)
WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),vcd,fst)
get_waveform_flag = +vcdfile=$(1).$(if $(filter $(USE_FST),0),vcd,fst)
#----------------------------------------------------------------------------------------
# verilation configuration/optimization
@@ -226,7 +226,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) $(sim_prefix)-*
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
clean-sim:
rm -rf $(model_dir) $(sim)

47
sims/xcelium/Makefile
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@@ -77,7 +77,6 @@ XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
#########################################################################################
# xcelium simulator rules
#########################################################################################
@@ -87,37 +86,35 @@ $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
$(sim_run_tcl): $(sim_workdir)
echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
echo "run" >> $(sim_run_tcl)
echo "exit" >> $(sim_run_tcl)
echo "$$CAD_INFO_HEADER" > $@
echo "run" >> $@
echo "exit" >> $@
# The system libstdc++ may not link correctly with some of our dynamic libs, so
# force loading the conda one (if present) with LD_PRELOAD
$(sim): $(sim_workdir) $(sim_run_tcl)
echo "#!/usr/bin/env bash" > $(sim)
echo "$$CAD_INFO_HEADER" >> $(sim)
cat arg-reshuffle >> $(sim)
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
chmod +x $(sim)
echo "#!/usr/bin/env bash" > $@
echo "$$CAD_INFO_HEADER" >> $@
cat arg-reshuffle >> $@
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
chmod +x $@
$(sim_debug_run_tcl): $(sim_workdir)
echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
echo "run" >> $(sim_debug_run_tcl)
echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
echo "exit" >> $(sim_debug_run_tcl)
echo "$$CAD_INFO_HEADER" > $@
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $@
echo "set probe_packed_limit 64k" >> $@
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $@
echo "run" >> $@
echo "database -close default_vcd_dump" >> $@
echo "exit" >> $@
$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
echo "#!/usr/bin/env bash" > $(sim_debug)
echo "$$CAD_INFO_HEADER" >> $(sim_debug)
cat arg-reshuffle >> $(sim_debug)
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
chmod +x $(sim_debug)
echo "#!/usr/bin/env bash" > $@
echo "$$CAD_INFO_HEADER" >> $@
cat arg-reshuffle >> $@
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $@
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
chmod +x $@
#########################################################################################
# create vcd rules
@@ -131,7 +128,7 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) $(sim_prefix)-*
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
clean-sim:
rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log

2
sims/xcelium/xcelium.mk
View File

@@ -1,5 +1,5 @@
WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd
get_waveform_flag=+vcdfile=$(1).vcd
# If ntb_random_seed unspecified, xcelium uses 1 as constant seed.
# Set ntb_random_seed_automatic to actually get a random seed