From bd49068eba4e2352e774688f93dc33d1c102da07 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 May 2023 09:28:25 -0700 Subject: [PATCH] Fix ManyPeripheralsRocketConfig' --- .../src/main/scala/config/PeripheralDeviceConfigs.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 9eec165e..db766a1e 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -65,13 +65,15 @@ class dmiRocketConfig extends Config( // DOC include end: DmiRocket class ManyPeripheralsRocketConfig extends Config( + new testchipip.WithBlockDevice ++ // add block-device module to peripherybus + new testchipip.WithOffchipBusManager(MBUS) ++ + new testchipip.WithOffchipBus ++ + new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new chipyard.config.WithSPIFlash ++ // add the SPI flash controller new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port - new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig)