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Fix NoCoresConfig with no PRCI features

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This commit is contained in:
Jerry Zhao
2023-06-01 18:43:34 -07:00
parent f758eb48a8
commit bb14a1f173
2 changed files with 11 additions and 9 deletions
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6
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
View File

@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_bus
clockSelector.tlNode := system.prci_ctrl_bus
pllCtrl.tlNode := system.prci_ctrl_bus
clockDivider.tlNode := system.prci_ctrl_bus.get
clockSelector.tlNode := system.prci_ctrl_bus.get
pllCtrl.tlNode := system.prci_ctrl_bus.get
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode

14
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
View File

@@ -21,7 +21,9 @@ case class ChipyardPRCIControlParams(
baseAddress: BigInt = 0x100000,
enableTileClockGating: Boolean = true,
enableTileResetSetting: Boolean = true
)
) {
def generatePRCIXBar = enableTileClockGating || enableTileResetSetting
}
case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
@@ -36,13 +38,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
prci_ctrl_domain.clockNode := tlbus.fixedClockNode
val prci_ctrl_bus = prci_ctrl_domain { TLXbar() }
tlbus.coupleTo("prci_ctrl") { (prci_ctrl_bus
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLFragmenter(tlbus.beatBytes, tlbus.blockBytes)
:= TLBuffer()
:= _)
}
})
// Aggregate all the clock groups into a single node
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
@@ -82,13 +84,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
val resetSynchronizer = prci_ctrl_domain { ClockGroupResetSynchronizer() }
val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
clock_gater.tlNode := prci_ctrl_bus
clock_gater.tlNode := prci_ctrl_bus.get
clock_gater
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
reset_setter.tlNode := prci_ctrl_bus
reset_setter.tlNode := prci_ctrl_bus.get
reset_setter
} }