diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst
index b63a3885..f86a118a 100644
--- a/docs/Advanced-Concepts/Chip-Communication.rst
+++ b/docs/Advanced-Concepts/Chip-Communication.rst
@@ -98,7 +98,7 @@ As a reminder, to run a software RTL simulation, run:
 If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication,
 then you must tie-off the serial-link interface, and instantiate the `SimDTM`.
 
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
     :language: scala
     :start-after: DOC include start: DmiRocket
     :end-before: DOC include end: DmiRocket
diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst
index 40b741d9..c3840297 100644
--- a/docs/Generators/SiFive-Generators.rst
+++ b/docs/Generators/SiFive-Generators.rst
@@ -31,7 +31,7 @@ This example instantiates a top-level module with include GPIO ports, and then t
 
 Finally, you add the relevant config fragment to the SoC config. For example:
 
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
     :language: scala
     :start-after: DOC include start: GPIORocketConfig
     :end-before: DOC include end: GPIORocketConfig