Rename implicit clock/reset to referenceclock/reset

2023-05-12 15:11:44 -07:00
parent 94d471bd9a
commit b8e95e0305
7 changed files with 20 additions and 20 deletions
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -114,12 +114,12 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
  val hReset = Wire(Reset())
  hReset := _outer.dutClock.in.head._1.reset

-  def implicitClock = _outer.dutClock.in.head._1.clock
-  def implicitReset = hReset
+  def referenceClock = _outer.dutClock.in.head._1.clock
+  def referenceReset = hReset
  def success = { require(false, "Unused"); false.B }

-  childClock := implicitClock
-  childReset := implicitReset
+  childClock := referenceClock
+  childReset := referenceReset

  instantiateChipTops()
 }